tdat04622 ETC-unknow, tdat04622 Datasheet - Page 121

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
UTOPIA (UT) Interface Block
UT Transmit Input Path (Egress)
In the transmit direction, data arrives from the various UTOPIA interfaces, and is stored in a 256-byte FIFO, one
per channel. After sufficient data has been stored into the FIFO, it is made available to be sent to the DE.
Like the UTOPIA Rx interface, the UTOPIA Tx interface is designed to accommodate ATM cells as well as packet
traffic. While the traditional UTOPIA interface only transfers ATM cells, this interface has been enhanced to carry
packet traffic. The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2
(U2+), UTOPIA Level 3 (U3) in 4 x 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 4 x 8-bit
mode or 32-bit mode.
The UTOPIA Tx side can indicate to the ATM side to suspend the transfer, by deasserting TxPA, when necessary.
When the amount of data in the FIFO exceeds its programmable high watermark, it deasserts TxPA. This signal
causes the deassertion of TxPA on the next clock. At this point, the ATM side knows that the UTOPIA Tx block can
only accept a limited number of words, after which it will overflow. In this case, the ATM device must not exceed
writing this limited number of words before suspending the transfer. Transfer is resumed once again when the
FIFO falls below the high watermark. When transferring ATM cells, TxPA must be deasserted four clocks before
the end of cell, or else it must be prepared to accept an entire new cell. When transferring ATM cells, deasserting
TxPA does not immediately suspend the transfer of the current cell because the entire cell can be transmitted with-
out interruption.
Transmit Cell/Packet Available (TxPA). This signal indicates when the TDAT042G5 transmit FIFO can accept
data from the master device. If the FIFO is empty or more than the provisioned space is available in the FIFO,
TxPA[D:A] is set active.
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* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.
One-Cycle Delay Mode. This mode follows the UTOPIA Level 2 Standard. The TxPA response occurs one cycle
after the address is polled.
Two-Cycle Delay Mode. This mode follows the UTOPIA Level 3 baselined text*. The TxPA response occurs two
cycles after the address is polled.
TxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on the UTOPIA provisionable watermarks. In
packet mode, TxPA[D:A] goes high when the amount of data in the FIFO is less than the high watermark setting.
In ATM mode, TxPA[D:A] goes high when the FIFO has space to receive a complete ATM cell from the master.
(This requires the high threshold to be set appropriately by the user, i.e., set so that an entire cell can be
received once TxPA[D:A] goes active.)
TxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low when the amount of data in the FIFO reaches or
exceeds the high watermark. In ATM mode, TxPA[D:A] goes low when there is not enough space in the FIFO to
receive an entire ATM cell. (This requires the threshold values to be provisioned properly, i.e., set low enough
such that when the high watermark is reached, the transmission of the current cell can be completed without
overflowing the FIFO). In ATM mode, TxPA[D:A] will be deasserted four cycles before the end of the current cell
transfer if the FIFO cannot accept a complete ATM cell on the following transmission.
TxPA[D:A] is updated on the rising edge of TxCLK[D:A].
In 32-bit mode, only the TxPA[A] pin of port A is used to indicate the packet/cell available status.
MPHY Support. When the TxPA signals are used for multi-PHY (MPHY) direct status, the corresponding
TxCLK[B, C, and/or D] must be provided. This clock will be the same as TxCLK[A].
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155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
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