tdat04622 ETC-unknow, tdat04622 Datasheet - Page 124

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
UTOPIA (UT) Interface Block
Multi-PHY Support
In addition to point-to-point UTOPIA mode, the TDAT042G5, as the slave device, can also be configured to support
the polled multi-PHY mode. To operate in multi-PHY mode, channel A must be configured in the polling mode,
since the control signals of channel A are used for all channels. Any combination of B, C, or D can be included in
the polling group, in which case they provide control information to channel A. Channels B, C, and D also can be
configured in any of the UTOPIA modes. In this case, the output is transferred through the channel A interface
(channel A and B interfaces for 32-bit mode). Channels not configured for polling can be operated as point-to-point
connections. If channel A is in 32-bit polling mode, channel B cannot be in point-to- point mode since its interface is
controlled by channel A, while channels C and D may be provisioned as point-to-point connections.
Figure 26 shows a multi-PHY mode when all four channels of the UT are in polling mode.
Mixed mode polling is also possible. For example, for those channels operated in polling mode, it is legitimate for
some of the channels to be in packet mode while others are in ATM mode. However, if one or more of the channels
are in packet mode, channel A should be configured as packet mode to activate control signals for packet transfer.
Multi-PHY operation can be configured by asserting the polling mode enable bit and Tx/Rx address in the respec-
tive port provisioning registers (see port provisioning registers, pages 158—161). Microprocessor provisionable
registers in each channel include a polling mode enable bit and 5-bit Rx address or 5-bit Tx address. The value for
the Tx and Rx address of an MPHY channel must be identical. Both the Rx and Tx directions have a 5-pin address
input to poll and select the appropriate PHY.
96
Figure 26. Multi-PHY Configuration of All Four Channels
µP
INGRESS CHANNEL A
INGRESS CHANNEL B
INGRESS CHANNEL C
INGRESS CHANNEL D
EGRESS CHANNEL A
EGRESS CHANNEL B
EGRESS CHANNEL C
EGRESS CHANNEL D
(continued)
(continued)
UTOPIA _PHY_Rx
UTOPIA _PHY_Rx
UTOPIA _PHY_Rx
UTOPIA _PHY_Rx
UTOPIA _PHY_Tx
UTOPIA _PHY_Tx
UTOPIA _PHY_Tx
UTOPIA _PHY_Tx
RxPA[A]/RxDATA[A]
RxENB[A]/RxADDR
TxPA[A]
TxENB[A]/TxDATA[A]/TxADDR
RxPA[B]
RxPA[C]
RxPA[D]
TxPA[B]
TxPA[C]
TxPA[D]
Agere Systems Inc.
Data Sheet
May 2001
5-7349(F)r.2