tdat04622 ETC-unknow, tdat04622 Datasheet - Page 34

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
Data Sheet
155/622/2488 Mbits/s Data Interface
May 2001
List of Figures
Contents
Page
Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View) .........................................................................................11
Figure 2. Overview Block Diagram .........................................................................................................................45
Figure 3. Interface Block Diagram ..........................................................................................................................46
Figure 4. External Interface Summary Diagram .....................................................................................................49
Figure 5. Functional Block Diagram .......................................................................................................................50
Figure 6. Signal Degrade and Failure Parameters for BER ...................................................................................56
Figure 7. Pointer Interpreter State Diagram ...........................................................................................................62
Figure 8. STS-48 Signal Carrying One STS-48c Frame ........................................................................................65
Figure 9. STS-48 Signal Carrying Four STS-12c Frames ......................................................................................66
Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame ..........................66
Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame (Channel A), One
STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and One STS-3c Frame (Channel D) .67
Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame ..............................67
Figure 13. Block Diagram of Date Engine (DE) ......................................................................................................70
Figure 14. State Diagram for the X31 Scrambler Synchronization Process ...........................................................72
Figure 15. General Structure of SDL Packets ........................................................................................................72
Figure 16. Uncompressed and Compressed PPP Packets ....................................................................................75
Figure 17. Example of Tx/Rx Sequencer Configuration: STS-48c into Single OC-48 Signal .................................78
Figure 18. Example of Tx/Rx Sequencer Configuration: 4xSTS-12c into Four Independent OC-12 Signals .........79
Figure 19. SONET Multiplexing: 2-Stage Byte Interleaving Example .....................................................................80
Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals .............81
Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X31) ................................................................................82
Figure 22. UT Block Diagram .................................................................................................................................84
Figure 23. Receive-Side Interface Handshaking in Point-to-Point, Single Cycle Mode .........................................91
Figure 24. Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode ............................................92
Figure 25. Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode ........................................95
Figure 26. Multi-PHY Configuration of All Four Channels ......................................................................................96
Figure 27. TxPA Two-Cycle Responses of a Multi-PHY for All Four Channels ...................................................... 98
Figure 28. RxPA Responses of a Multi-PHY for All Four Channels (PA Response Configured for One Cycle) ....99
Figure 29. GPIO Functionality ..............................................................................................................................102
Figure 30. Interrupt Functionality ..........................................................................................................................103
Figure 31. Miscellaneous Functionality ................................................................................................................104
Figure 32. Loopback Operation ............................................................................................................................106
Figure 33. Quad ATM UTOPIA 2 ..........................................................................................................................107
Figure 34. Single ATM UTOPIA 3 ........................................................................................................................108
Figure 35. Quad POS UTOPIA 2 ..........................................................................................................................109
Figure 36. Single POS UTOPIA 3 ........................................................................................................................110
Figure 37. 32-bit MPHY UTOPIA 3 .......................................................................................................................110
Figure 38. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin D8) = 1) ....................................256
Figure 39. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin D8) = 1) ...................................258
Figure 40. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin D8) = 0) ...............260
Figure 41. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ..................................262
Figure 42. Receive Line-Side Timing Waveform ..................................................................................................264
Figure 43. Transmit Line-Side Timing Waveform—STS-48/STM-16 Contraclocking ...........................................265
Figure 44. Transmit Line-Side Timing Waveform—Frame Synch ........................................................................265
Figure 45. Transmit Line-Side Timing Waveform—STS-48/STM-16 Forward Clocking ......................................265
Figure 46. Transmit UTOPIA Interface Timing .....................................................................................................268
Figure 47. Receive UTOPIA Interface Timing ......................................................................................................269
Figure 48. Transmit TOAC Interface Timing .........................................................................................................271
Figure 49. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing ...............................................272
Figure 50. STS-3/STM-1 Receive TOAC Interface Timing ...................................................................................272
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