tdat04622 ETC-unknow, tdat04622 Datasheet - Page 261

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Register Descriptions
DE Registers
Table 133. Register 0x10AB: ATM Receive Debug Register (R/W)
Reset default of register = 0x003C.
Address
(Hex)
10AB
15—6
(continued)
Bit #
—
5
4
3
2
1
0
ATM_Rx_DEBUG_REG[5:0]
(continued)
Name
—
—
—
—
—
—
—
ATM Receive Debug Register.
Reserved. These bits must be written to their
reset default value (0000000000).
Channel 3 All Cool-Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.
Channel 2 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.
Channel 1 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.
Channel 0 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.
Incrementing NULL Cell Payload Sequence.
This bit governs whether 0x6A is used for the
payload of NULL cells, or whether an
incrementing 8-bit count is used (0x00 →
0xFF). A value of 1 selects the incrementing
sequence. This can be used with the All_Cool
interrupt.
X31_Sync_Compare. In X
value is 0, the ATM framer does 6-bit
comparisons of the HEC, which does not allow
for error correction. When this value is 1, all 8
bits of the HEC are used, which does allow for
error correction.
155/622/2488 Mbits/s Data Interface
Function
31
mode, when this
TDAT042G5 SONET/SDH
0x003C
Default
Reset
0000
0000
00
1
1
1
1
0
0
233