tdat04622 ETC-unknow, tdat04622 Datasheet - Page 133

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Interface Description
Performance Monitor Reset (PMRST)
Address 0x0010, bits 8 and 9 of the core register set defines the mode of operation for PMRST. Address 0x000E,
bit 7 provides the software-controllable reset function (see Register Maps section, page 112). When this bit is set
to 1, the PMRST signal goes high. The register will automatically be reset to 0, and the PMRST signal will go low
after 500 ms.
Table 32. PMRST Provisioning
ADDR 0x0010, Bits 9, 8
Core Register
00
01
11
PMRST comes from external pin (1 Hz, 50% duty cycle signal).
PMRST comes from internal 1-second counter (1 Hz, 50% duty cycle signal).
Writing a logic 1 to the PMRST bit (core register 0x000E, bit 7) in this mode will
reset the counter so that a 0→1 transition occurs on the PMRST within 10 clock
cycles of the 77.76 MHz clock.
PMRST is software controlled. Writing a logic 1 to the PMRST bit (core register
0x000E, bit 7) will cause a 0→1 transition on the internal PMRST signal. This
pulse will be high for 100 cycles of the 77.76 MHz clock and low for 100 cycles of
the 77.76 MHz clock. Writing the PMRST bit to a logic 1 during this 200 clock
cycle interval will have no effect (2.57 µs). The PMRST rising edge must occur
within 10 clock cycles of writing the PMRST bit.
(continued)
(continued)
Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
105