tdat04622 ETC-unknow, tdat04622 Datasheet - Page 88

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
Overhead Processor (OHP) Block
Receive OHP (continued)
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Transmit OHP
Overhead Insertion. Some transport overhead (TOH) bytes can optionally be inserted via the TxTOH interface
and inserted into the TOH bytes (see Table 15, page 53). Certain bytes can be either inserted from values stored in
registers or automatically generated. The TxTOH interface controls the insertion mechanism. Software insertion
takes precedence over TOAC insertion. The number of bits received are as follows:
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S1 Synchronization Message. The S1 block controls the insertion of the S1 byte. The byte ordering is the same
as the RxTOAC and is shown in Table 18 (see pa ge59). The S1 byte can be provisioned to come from the TxTOH
interface or from a software-settable register. Control for message insertion is from software control register
TS1INS[A—D] (see register description, page 179 and page 183).
K1K2 APS Signaling. The APS block controls the insertion of the K bytes based on software provisioned K bytes,
and alarm conditions (AIS-L, RDI-L). Inconsistent APS bytes can be inserted via register provisioning by
TAPSBABBLEINS[A—D] (see register description, page 178 and page 183).
RDI_L Generation. The following six alarms contribute to RDI_L generation: LOF, OOF, LOS, LOC, AIS_L, and
SF. They can be inhibited from contributing to RDI-L via transmit control registers (addresses 0x042F, 0x0431,
0x0433, 0x0435; see register description, page 180).
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Rx Synchronization Message. The S1 block filters the synchronization message (S1) byte and stores the vali-
dated message in a software-accessible register. The synchronization message will be validated if a programma-
ble number (in OHP register CNTDS1) of consecutive frames contain identical S1 values. An inconsistent
synchronization message alarm will be reported if a provisional number (by OHP register CNTDS1FRAME) of
consecutive frames pass without a validated message occurring. (See page 172 for register descriptions of
CNTDS1[A—D][3:0] and CNTDS1FRAME [A—D][3:0].)
F1 User Channel. The F1 byte is extracted by the OHP . The F1 user channel is monitored for change of state
using OHP registers 0x0402, 0x0404, 0x0406, 0x0408 (see register map, page 116). The previous and current
F1 values are stored in F1DMON1[A—D][7:0] and F1DMON0[A—D][7:0], respectively (see page 122 for register
map, page 190 for register descriptions).
DCC and Orderwire Bytes. The data communication channel (D1—D3, D4—D12) and orderwire bytes (E1, E2)
can only be extracted via the TOAC.
D1/D2/D3 Section Data Communications Channels (DCC). DCC outputs are taken from the TOAC.
D4—D12 Line Data Communications Channels (DCC). DCC outputs are taken from the TOAC.
M1 REI-L. REI-L is extracted by the OHP.
Support for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over-
fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead
insertion/extraction is done when in bypass mode.
STS-3/STM-1: 5,184,000 bits/s per interface
STS-12/STM-4: 20,736,000 bits/s per interface
STS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))
(continued)
(continued)
Agere Systems Inc.
Data Sheet
May 2001