tdat04622 ETC-unknow, tdat04622 Datasheet - Page 73

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Overview
This device integrates the SONET/SDH interface termination functions with a generic cell/packet delineation cir-
cuit. It supports STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1 interface rates. Up to four data
channels transported within an STS-N payload are processed via the SONET/SDH termination blocks and the on-
chip data encapsulation/decapsulation engine. Packet or ATM data are transmitted/received by this device on the
equipment side via the enhanced UTOPIA interface. SONET/SDH streams are transmitted/received by this device
on the network side via the line interface.
Concatenation levels supported by this device range from STS-1 to STS-48c. Valid standard concatenated
SONET frame configurations for this device are STS-3c, STS6c, STS-9c, STS-12c, STS-15c, STS-18c, and STS-
48c. Non-standard concatenation levels (such as STS-4c, STS-5c, STS-7c, etc.) are supported as well. In STS-48
mode, four pointer processors are available. This allows an STS-48 frame to carry up to four concatenated sub-
frames (for example, mapping of four STS-12c payloads into an STS-48 frame). In quad STS-3 and STS-12
modes, only one pointer processor is available. Therefore, only a single subframe may be mapped into an STS-3
or STS-12 frame (mapping a single STS-3c payload into an STS-12 frame, for instance). For details, see Table 22
on page 68.
This device supports mapping for ATM cells into SONET/SDH, mapping for packet data via all existing or currently
proposed standards (e.g., PPP, SDL) into SONET/SDH streams. Via SDL mapping, this device also supports
packet over fiber or ATM over fiber, respectively. Figure 2 shows the overview block diagram, and Figure 3 shows
the interface block diagram for this device.
OR QUAD STM-4/STS-12
OR QUAD STM-4/STS-12
SINGLE STM-16/STS-48
SINGLE STM-16/STS-48
OR QUAD STM-1/STS-3
OR QUAD STM-1/STS-3
TERMINATION
PROCESSOR
PROCESSOR
OVERHEAD
OVERHEAD
MONITOR
Figure 2. Overview Block Diagram
INSERT
LINE
TERMINATION
µP INTERFACE
INTERPRETER
CONTROL
POINTER
MAPPER
PATH
SPE
PACKET/CELL
PROCESSOR
-ENCAPSULATION
-SCRAMBLING
-CRC GENERATION
PACKET/CELL
PROCESSOR
-DELINEATION
-DECAPSULATION
-UNSCRAMBLING
-CRC VERIFICATION
TERMINATION
PAYLOAD
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
(U2, U2+, U3, U3+)
COMPATIBLE
INTERFACE
ENHANCED
UTOPIA
INTERFACE
5-6680(F).ar.15
ENHANCED
UTOPIA
45