tdat04622 ETC-unknow, tdat04622 Datasheet - Page 27

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

May 2001
Agere Systems Inc.
AY99-013SONT-2 Replaces AY99-013SONT to Incorporate the Following Updates
1. Page 1, SP1. Required Provisioning Sequence and Clocks, added new issue.
2. Page 8, DE4. Channel Provisioning, added new issue.
3. Page 9, DE5. Packet Behavior in POS/SDL Mode—Dry Mode, added new issue.
4. Page 15, UT8. Far-End Loopback Bandwidth Limitations, added new issue.
5. Page 16, advance data sheet document number corrected.
AY99-013SONT-3 Replaces AY99-013SONT-2 to Incorporate the Following Updates
1. Page 1, notice that the advisory issues still apply to the advance data sheet which has just been updated.
AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates
1. Replaced OC- designation with STS- and STM- throughout advisory.
2. Page 2, SP2. Behavior During Loss of Receive Line Clock, added new issue.
3. Page 2, SP3. PT Register Addressing, added new issue.
4. Page 4, CR1. Clear on Read/Clear on Write Behavior, added new issue.
5. Page 5, PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits, corrected description.
6. Page 6, PT4. SS Pointer Interpretation Algorithm, added new issue.
7. Page 7, PT5. Delta/Event Registers in COR Mode, added new issue.
8. Page 7, DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation, identified the specific ITU stan-
9. Page 8, DE4. Channel Provisioning, Table Transmit DE Egress and Sequencer Cell State Registers, corrected
10. Page 9, DE5. Packet Behavior in POS/SDL Mode—Dry Mode, identified dry mode issues.
11. Page 10, DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation, added new issue.
12. Page 10, DE7. Incorrect Frame State of ATM Data Streams, added new issue.
13. Page 11, DE8. Clearing DE Interrupt Register (0x1002), added new issue.
14. Page 11, DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes, added new issue.
15. Page 12, DE10. Excessive HDLC Flag Characters, added new issue.
16. Page 13, UT2. UTOPIA Clock Limitations, clarified wording.
17. Page 14, UT4. FIFO Overflow and Error Reporting, clarified wording.
18. Page 16, UT9. Clock Requirements for MPHY Modes, added new issue.
19. Page 16, UT10. Egress Packet Mode Overflows, added new issue.
20. Page 17, UT11. Clearing UT Interrupt Register, added new issue.
21. Page 17, UT12. Incorrect Implementation of POS Multi-PHY Mode, added new issue.
22. Page 21, OHP1. Maximum BER Count, added new issue. In addition, differentiated OHP bits from PT bits with
dard with which the LCD implementation does not comply.
register 0x102D to 0x1021.
the same name; the names will be corrected in revision 4 of the advance data sheet.
for Version 1 and 1A of the Device
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