tdat04622 ETC-unknow, tdat04622 Datasheet - Page 59

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Pin Information
Table 5
AP18
AN30
AA34
AP19
AP31
AR17
AP30
AA33
H33
G34
H34
Y33
Pin
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
TxENB[D]
TxENB[C]
TxENB[B]
TxENB[A]
TxCLK[D]
TxCLK[C]
TxCLK[B]
TxCLK[A]
Symbol
TxPA[D]
TxPA[C]
TxPA[B]
TxPA[A]
(continued)
(5 V tolerant)
(5 V tolerant)
3.3 V
3.3 V
3.3 V
Type
I/O
O
I
I
Transmit Cell/Packet Available. (continued)
I
I
Transmit Clock. This clock is used to write cells or packets into
the transmit FIFO. TxCLK[D:A] can operate at speeds from dc to
104 MHz.
In U3 or U3+ (32-bit mode), only the TxCLK[A] input pin of port A
is used to clock the data input.
If MPHY direct status is used, then all clocks TxCLK[D:A] must be
provided.
Transmit Data Enable (Active-Low). This signal is used to trans-
fer data on the TxDATA[D:A][15:0] bus into the transmit FIFOs. If
TxENB[D:A] is high, no operation is performed. If TxENB[D:A] is
low, a write occurs.
TxENB[D:A] is sampled on the rising edge of TxCLK[D:A].
TxENB[D:A] has the same meaning as data valid.
In U3 or U3+ (32-bit mode), only the TxENB[A] input pin of port A
is used to enable the transfer of data.
TxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low
when the amount of data in the FIFO reaches or exceeds the
high watermark. In ATM mode, TxPA[D:A] goes low when there
is not enough space in the FIFO to receive an entire ATM cell.
(This requires the threshold values to be provisioned properly,
i.e., set low enough such that when the high watermark is
reached, the transmission of the current cell can be completed
without overflowing the FIFO). In ATM mode, TxPA[D:A] will be
deasserted four cycles before the end of the current cell trans-
fer if the FIFO cannot accept a complete ATM cell on the follow-
ing transmission.
MPHY Support. When the TxPA signals are used for multi-PHY
(MPHY) direct status, the corresponding TxCLK[B, C, and/or D]
must be provided. This clock will be the same as TxCLK[A].
TxPA[D:A] is updated on the rising edge of TxCLK[D:A].
In 32-bit mode, only the TxPA[A] pin of port A is used to indicate
the packet/cell available status.
Name/Description
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
31