tdat04622 ETC-unknow, tdat04622 Datasheet - Page 112

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
UTOPIA (UT) Interface Block
The UT core provides buffering and UTOPIA interface functionality. This enhanced UTOPIA interface will pass U2,
U2+, U3, and U3+ protocols. In the receive direction, data is buffered from the line side, and sent out of the device
via a UTOPIA/packet-over-SONET-PHY interface. In the transmit direction, data is received by the device via a
UTOPIA/packet-over-SONET-PHY interface, and buffered before being sent to the line side. Data that is sent or
received can be either packet or ATM traffic, and is configurable on a per-channel basis. The UTOPIA slave inter-
face is designed to accommodate back-to-back ATM cell and packet data transfers in point-to-point or multi-PHY
modes.
Level-2 physical interfaces (transmit and receive) support four logical data channels as shown in Figure 22. Each
of these interfaces is independently configurable for cell or packet transfers, and can support up to STS-12/STM-4
bandwidth. Optionally, two of the interfaces, specifically A and B, can be grouped together to support a 32-bit
UTOPIA level-3 interface supporting up to STS-48/STM-16 of bandwidth. The aggregate traffic that can be carried
over these interfaces is limited to STS-48/STM-16 bandwidth.
In addition to operating as separate point-to-point streams, MPHY capabilities for up to four channels can be pro-
vided from the A interface in either 16-bit or 32-bit modes. For example, when operating as a 32-bit interface, the A
interface can support either a single STS-48c channel or four STS-12c channels. As a 16-bit interface, the MPHY
interface can support either a single STS-12c channel or four STS-3c channels.
Since each channel can be configured independently, each one can carry different traffic types at different rates,
provided that the capabilities of the active interfaces and the data engine are not exceeded.
There are two basic data paths: receive side, defined to be data going from the line side to the UTOPIA side, and
transmit side, defined to be data going from the UTOPIA side to the line side as shown in Figure 22.
Note: For MPHY support, channels are mapped to interface A only.
84
(continued)
Tx
Rx
LOOPBACKS
Figure 22. UT Block Diagram
IN BOTH DIRECTIONS (Tx & Rx)
COMBINES CHANNELS A & B
NOTE: UTOPIA 32-bit MODE
SOFTWARE REGISTERS
UTOPIA 2/3 INTERFACE
INGRESS SIDE
EGRESS SIDE
INTERFACE A
INTERFACE B
INTERFACE C
INTERFACE D
INTERFACE A
INTERFACE B
INTERFACE C
INTERFACE D
INTERNAL
CONTROL
BUS
Agere Systems Inc.
Data Sheet
May 2001
5-7056(F)r.5