tdat04622 ETC-unknow, tdat04622 Datasheet - Page 36

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Contents
TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration .......................................................................152
Table 53. Register 0x001F: Scratch (R/W) ...........................................................................................................153
Table 54. Register 0x0200: UT Macrocell Version Number (RO) ........................................................................154
Table 55. Register 0x0201: UT Interrupt (RO) .....................................................................................................154
Table 56. Registers 0x0202, 0x0203, 0x0204, 0x0205: Channel [A—D] (COR) ..................................................155
Table 57. Register 0x0206: Interrupt Mask (R/W) ................................................................................................156
Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask—Channel [A—D] (R/W) ........................156
Table 59. Register 0x020B: Channel [A—D] Error Count in PMRST Mode (RO) ................................................156
Table 60. Fields of the Provisioning Registers .....................................................................................................157
Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A—D] Receive Provisioning Register (R/W) .158
Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A—D] Transmit Provisioning Register (R/W) 159
Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A—D] Ingress Provisioning Register (R/W) ..161
Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A—D] Egress Provisioning Register (R/W) ...161
Table 65. Register 0x021F: Reset Register (R/W) ...............................................................................................162
Table 66. Register 0x0220: Channel [A—D] Error Count (RO) ............................................................................162
Table 67. Register 0x0224: UT_Scratch Register (R/W) ......................................................................................162
Table 68. Register 0x0225: PA Response Register (R/W) ...................................................................................163
Table 69. Register 0x0226: Size Mode Register (R/W) ........................................................................................164
Table 70. Register 0x0400: OHP Macrocell Version Number (RO) .....................................................................165
Table 71. Register 0x0401: OHP Interrupt (RO) ..................................................................................................165
Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W) ..............................................................................165
Table 73. Registers 0x040A—0x040D: Receive/Transmit State (RO) .................................................................168
Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W) ............................................................169
Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W) ............................................................170
Table 76. Registers 0x0416—0x0419: Toggles (R/W) .........................................................................................171
Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W) .....171
Table 78. Registers 0x041B, 0x041D, 0x041F, 0x0421: Continuous N Times Detect (CNTD) Values (R/W) .....172
Table 79. Registers 0x0422—0x042D: Receive Control (R/W) ............................................................................173
Table 80. Registers 0x042E: Transmit Control Port A (R/W) ...............................................................................177
Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W) .................................................180
Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) ............................................181
Table 83. Registers 0x0436—0x0439: Transmit Control (R/W) ...........................................................................184
Table 84. Registers 0x043A—0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W) ........................185
Table 85. Registers 0x0452—0x0469: OHP Signal Fail BER Algorithm Parameters (R/W) ................................186
Table 86. Ns, L, M, and B Values to Set the BER Indicator .................................................................................187
Table 87. Ns, L, M, and B Values to Clear the BER Indicator ..............................................................................188
Table 88. Registers 0x046A—0x047D: B1, B2, M1 Error Count (RO) .................................................................189
Table 89. Registers 0x047E—0x0485: Transmit F1, S1, K2, K1 OH Insert Value (R/W) ....................................189
Table 90. Registers 0x0486—0x0491: Receive F1, S1, K2, K1 Monitor Value (RO) ...........................................190
Table 91. Registers 0x0492—0x04F9: Receive J0 Monitor Value (RO) ..............................................................190
Table 92. Registers 0x0512—0x0579: Transmit J0 Insert Value (R/W) ...............................................................190
Table 93. Registers 0x05AA—0x05C1: Transmit Z0 Insert Value (R/W) .............................................................191
Table 94. Register 0x05C2: Scratch Register (R/W) ............................................................................................191
Table 95. Register 0x0800: PT Macrocell Version Number (RO) .........................................................................192
Table 96. Register 0x0801: PT Interrupt (RO) ......................................................................................................192
Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A:
Table 98. Registers 0x0836—0x083B, 0x0868—0x0887, 0x0888—0x088D, 0x08BA—0x08D9,
Table 99. Register 0x097E: PT Interrupt Mask Control (R/W) .............................................................................195
8
PT Delta/Event Parameters (COR/W) ..................................................................................................192
0x08DA—0x08DF, 0x090C—0x092B, 0x092C—0x0931, 0x095E—0x097D:
PT State Registers (RO) ......................................................................................................................194
List of Tables
(continued)
Agere Systems Inc.
Data Sheet
May 2001
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