tdat04622 ETC-unknow, tdat04622 Datasheet - Page 56

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Note: An external pull-up resistor of 50 kΩ—100 kΩ is required on all input pins of a disabled UTOPIA port. Either
Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals
28
AM31
AD35
AD34
AD33
AD32
AD31
AB34
AB33
AB31
AB32
AC34
AC33
AC32
AC31
AE35
AE34
AE33
W34
M31
M32
M33
M34
M35
Y34
G33
G32
K31
K32
K33
K34
K35
L32
L33
L34
L35
Pin
J34
J35
an external pull-up resistor of 50 kΩ—100 kΩ or an external pull-down resistor of 0 Ω—1 kΩ is required on all
unused inputs of an enabled UTOPIA port. Use of either a pull-up or pull-down resistor is selected to place
the unused input pin into the inactive state.
TxDATA[A][15]
TxDATA[A][14]
TxDATA[A][13]
TxDATA[A][12]
TxDATA[A][11]
TxDATA[A][10]
TxDATA[B][15]
TxDATA[B][14]
TxDATA[B][13]
TxDATA[B][12]
TxDATA[B][11]
TxDATA[B][10]
TxDATA[A][9]
TxDATA[A][8]
TxDATA[A][7]
TxDATA[A][6]
TxDATA[A][5]
TxDATA[A][4]
TxDATA[A][3]
TxDATA[A][2]
TxDATA[A][1]
TxDATA[A][0]
TxDATA[B][9]
TxDATA[B][8]
TxDATA[B][7]
TxDATA[B][6]
TxDATA[B][5]
TxDATA[B][4]
TxDATA[B][3]
TxDATA[B][2]
TxDATA[B][1]
TxDATA[B][0]
TxADDR[4]
TxADDR[3]
TxADDR[2]
TxADDR[1]
TxADDR[0]
Symbol
(continued)
(5 V tolerant)
(5 V tolerant)
(5 V tolerant)
Type
3.3 V
3.3 V
3.3 V
I/O
I
I
I
Transmit Address. The TxADDR is driven by the UTOPIA mas-
ter to poll and select the appropriate PHY channel of
TDAT042G5 to transmit data.
Note: The PHY address (0x00 to 0x1E) for each of the four
Transmit Data Channel A. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[A] is only valid when TxENB[A]
is asserted, and is sampled on the rising edge of TxCLK[A].
Note that TxDATA[A] is used in various UTOPIA modes. In U2 or
U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits 15
to 8 are valid.
In U3 or U3+ (32-bit mode), TxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16), and
TxDATA[B][15:0] forms the least significant 16 bits of the com-
bined data bus (bits 15 to 0).
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
Transmit Data Channel B. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[B] is only valid when TxENB[B]
is asserted (TxENB[A] for U3 or U3+ (32-bit mode)), and is sam-
pled on the rising edge of TxCLK[B] (TxCLK[A] for U3 or U3+
(32-bit mode). Note that TxDATA[B] is used in various UTOPIA
modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-bit
mode), only bits 15 to 8 are valid.
In U3 or U3+ (32-bit mode), TxDATA[B][15:0] forms the least sig-
nificant 16 bits of the combined data bus (bits 15 to 0), and
TxDATA[A][15:0] forms the most significant 16 bits of the com-
bined data bus (bits 31 to 16). In this mode, channel B port must
be provisioned to the idle (default) state.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
channels in TDAT042G5 is configured via software
provisioning.
Name/Description
Agere Systems Inc.
Data Sheet
May 2001