tdat04622 ETC-unknow, tdat04622 Datasheet - Page 123
tdat04622
Manufacturer Part Number
tdat04622
Description
Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
Manufacturer
ETC-unknow
Datasheet
1.TDAT04622.pdf
(310 pages)
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Data Sheet
May 2001
Agere Systems Inc.
Functional Description
UTOPIA (UT) Interface Block
UT Transmit Path (Egress) (continued)
Figure 25 illustrates the transmit-side interface handshaking when operating in point-to-point mode with the TxPA
response provisioned to be a single cycle. In two-cycle mode, the TxPA signal is delayed an additional cycle. In the
figure, the master device initiates the transfer after observing an asserted packet available for the channel by
asserting the TxENB signal. The master places data and start of packet on the bus the same cycle as TxENB, and
the TDAT042G5 samples the TxSOP and TxDATA on the following clock cycle (rising edge).
In this example, the master stops transfer in the middle of the packet. Data with value c is valid on the cycle that
TxENB goes inactive, and when TxENB returns, data is again valid on the first cycle (data value d).
The packet transfer is complete when the master asserts the TxEOP signal. If an error occurs in the packet, then
the TxERR signal is asserted simultaneously with the TxEOP. TxERR is ignored if it is not asserted when TxEOP
is active.
TxDATA[15:8]
TxSOP/C
TxEOP
TxERR
TxENB
TxCLK
TxPA
Figure 25. Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode
1
2
3
(continued)
(continued)
a
4
b
5
6
c
7
155/622/2488 Mbits/s Data Interface
8
d
9
TDAT042G5 SONET/SDH
e
10
f
11
g
12
5-7457(F).ar.2
95
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