tdat04622 ETC-unknow, tdat04622 Datasheet - Page 288

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Interface Timing Specifications
Microprocessor Interface Timing
Asynchronous Mode
The asynchronous microprocessor interface mode is selected when MPMODE (pin D8) = 0. Interface timing for the
asynchronous mode write cycle is given in Figure 40 and in Table 165 (see pages 260—261), and for the read
cycle in Figure 41 and in Table 166 (see pages 262—263).
ADDR[15:0] The address must be valid when ADS is low.
DATA[15:0]
R/W (Input)
CS (Input)
DT (Output) Data transfer acknowledge (active-low). DT is driven asynchronously based on the arrival of CS.
ADS (Input) Address strobe is active-low. The microprocessor can pull ADS high after DT goes high.
DS (Input)
260
Figure 40. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin D8) = 0)
ADDR[15:0]
DATA[15:0]
(INPUT)
Data must be valid when DS is low.
The read (H) write (L) signal is always high except during a write cycle.
Chip select is an active-low signal.
DT is driven high until the internal transaction is done. DT is driven high again when ADS is deas-
serted. DT will become 3-stated when CS is high.
Data strobe is active-low.
ADS
R/W
CS
DS
DT
HIGH Z
t19
t27
t17
t21
t23
(continued)
(continued)
t25
t28
t22
t24
t26
t29
t20
t18
t30
HIGH Z
Agere Systems Inc.
Data Sheet
May 2001
5-7661(F)r.3