tdat04622 ETC-unknow, tdat04622 Datasheet - Page 291

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Interface Timing Specifications
Microprocessor Interface Timing
Asynchronous Mode (continued)
Table 166. Microprocessor Interface Asynchronous Read Cycle Specifications
(See Figure 41 on page 262 for the timing diagram.)
Reset
Software Reset. Writing the binary value 101 to SWRST (core register 0x000E, bits 2—0) causes a 0 to 1 transi-
tion on the internal PMRST signal. This pulse will be high for 100 clock cycles and then low for 100 clock cycles of
the 77.76 MHz internal clock. Writing a logic 1 to these bits during this 200 clock-cycle interval (2.57 µs) has no
effect.
Interrupt. Occurrence of an interrupt is event driven. The interrupt pin, INT (B7), will be deasserted after a mini-
mum of either one MPU clock cycle in the synchronous microprocessor mode or 13 ns in the asynchronous micro-
processor mode after clearing the interrupt register.
Symbol
t31
t32
t33
t34
t35
t36
t37
t38
t39
t40
t41
t42
CS Fall to DS Fall
ADDR Invalid to CS Rise
ADDR Valid to ADS Fall
ADS Rise to ADDR Invalid
ADDR Valid to DS Fall
DS Rise to ADDR Invalid
CS Fall to DT High
DS Fall to DT Fall
ADS Rise to DT Rise
CS Rise to DT 3-state
DT Valid to DATA Valid
ADS Rise to DATA 3-state
Parameter
(continued)
(continued)
Min Interval
(ns)
90
—
—
0
0
0
5
0
0
0
0
0
155/622/2488 Mbits/s Data Interface
Max Interval
37.5
(ns)
115
12
—
—
—
—
—
—
—
—
—
TDAT042G5 SONET/SDH
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