tdat04622 ETC-unknow, tdat04622 Datasheet - Page 35

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
Data Sheet
155/622/2488 Mbits/s Data Interface
May 2001
List of Tables
Contents
Page
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order .......................................................................12
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name ...............................................................................17
Table 3. Pin Descriptions—Line Interface Signals .................................................................................................22
Table 4. Pin Descriptions—TOH Interface Signals .................................................................................................27
Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals ..........................................................................28
Table 6. Pin Descriptions—Microprocessor Interface Signals ................................................................................40
Table 7. Pin Descriptions—General-Purpose I/O Signals: Interface Signals .........................................................41
Table 8. Pin Descriptions—JTAG Interface Signals ...............................................................................................42
Table 9. Pin Descriptions—Power Signals .............................................................................................................43
Table 10. Pin Descriptions—No Connect Pins .......................................................................................................44
Table 11. Optional Offset Field ...............................................................................................................................48
Table 12. Line Interface Modes ..............................................................................................................................51
Table 13. Clock Settings for CLKDIV Pin ...............................................................................................................52
Table 14. R/T TOH Interface Rates ........................................................................................................................53
Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example ..................................................................................53
Table 16. Ns, L, M, and B Values to Set the BER Indicator ...................................................................................57
Table 17. Ns, L, M, and B Values to Clear the BER Indicator ................................................................................58
Table 18. TOAC Channel I/O vs. STS Number/Time Slot ......................................................................................59
Table 19. Types of Signal Labels ...........................................................................................................................64
Table 20. 1-bit Mode ...............................................................................................................................................64
Table 21. 3-bit Mode (Enhanced RDI) ....................................................................................................................64
Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c ........................................................68
Table 23. Packet Length Field ................................................................................................................................73
Table 24. UTOPIA Traffic Types ............................................................................................................................85
Table 25. Standard 53-byte ATM Cell Structure .....................................................................................................86
Table 26. Bus Format for 16-bit Interface ...............................................................................................................86
Table 27. Bus Format for 8-bit Interface .................................................................................................................87
Table 28. Bus Format for 32-bit Interface ...............................................................................................................87
Table 29. Egress High Watermark Thresholds .......................................................................................................94
Table 30. Nominal dc Power for Suggested Terminations ...................................................................................100
Table 31. MPU Modes ..........................................................................................................................................101
Table 32. PMRST Provisioning ............................................................................................................................105
Table 33. Quad ATM UTOPIA 3 Interface ............................................................................................................107
Table 34. Quad POS UTOPIA 3 Interface ............................................................................................................109
Table 35. Register Address Space .......................................................................................................................111
Table 36. Map of Core Registers ..........................................................................................................................112
Table 37. Map of UT Registers .............................................................................................................................113
Table 38. Map of OHP Registers ..........................................................................................................................116
Table 39. Map of Path Terminator Registers ........................................................................................................126
Table 40. Map of DE Registers ............................................................................................................................138
Table 41. Register 0x0000: Device Version (RO) ................................................................................................147
Table 42. Registers 0x0001—0x0005: Device Name (RO) ..................................................................................147
Table 43. Register 0x0008: Composite Interrupts (RO or COR/W) ......................................................................148
Table 44. Register 0x000A: GPIO Input (RO) ......................................................................................................148
Table 45. Register 0x000C: Block Interrupt Masks (R/W) ....................................................................................149
Table 46. Register 0x000E: Core Resets (WO) ...................................................................................................149
Table 47. Register 0x000F: GPIO Output (R/W) ..................................................................................................150
Table 48. Register 0x0010: Line Provisioning/Mode (R/W) ..................................................................................150
Table 49. Register 0x0011: Channel (A—D) Control (R/W) .................................................................................151
Table 50. Register 0x0012: Loopback Control (R/W) ...........................................................................................151
Table 51. Register 0x0013: GPIO Mode (R/W) ....................................................................................................152
Agere Systems Inc.
7