tdat04622 ETC-unknow, tdat04622 Datasheet - Page 228

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Register Descriptions
PT Registers
Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5: PT Con-
Reset default of registers 0x0AA6, 0x0AAE, 0x0AB6, 0x0ABE = 0xF200.
Reset default of registers 0x0AA7, 0x0AAF, 0x0AB7, 0x0ABF = 0x0000.
Reset default of registers 0x0AA8, 0x0AB0, 0x0AB8, 0x0AC0 = 0x0FFF.
Reset default of registers 0x0AA9, 0x0AB1, 0x0AB9, 0x0AC1 = 0x0000.
Reset default of registers 0x0AAA, 0x0AB2, 0x0ABA, 0x0AC2 = 0x0000.
Reset default of registers 0x0AAB, 0x0AB3, 0x0ABB, 0x0AC3 = 0x1AAA.
Reset default of registers 0x0AAC, 0x0AB4, 0x0ABC, 0x0AC4 = 0x3AAA.
Reset default of registers 0x0AAD, 0x0AB5, 0x0ABD, 0x0AC5 = 0x3333
* SS pointer interpretation algorithm is not implemented.
† These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed
200
0AA6, 0AAE,
0AA7, 0AAF,
0AB6, 0ABE
0AB7, 0ABF
through the DE. These bits do not affect the transmit path and do not affect the transmitted G1 byte.
Address
(Hex)
trol Parameters (R/W) (continued)
15—12
11—0
(continued)
Bit #
2—1
6
5
4
3
0
RDIPMON_ENH_OR1B
RB3BITBLKCNT[A—D]
CONCATI_EXPECTED
RINCDEC_6OR8MAJ
RFORCE_LOP[A—D]
RJ1DMPC[A—D]
[A—D][1—12]
(continued)
[A—D]
[A—D]
Name
[1—4]
—
—
Receive J1 Dump Control. Control bit, when set
to a logic 1, causes the device to store the J1 byte
of the selected STS-1 time slot.
Reserved. This bit must be written to its reset
default value (0).*
Receive B3 Bit/Block Count. Control bit, when
set to a logic 0, causes the B3 error counter to
count bit errors; otherwise, block errors are
counted.
Receive Increment/Decrement 6-or-8 Majority
Voting. If programmed to a logic 0, uses 6 of 10
majority voting to determine a valid increment or
decrement; otherwise, uses 8 of 10 majority voting.
Reserved. These bits must be written to their reset
default value (00).
Remote Defect Indication Enhanced or 1-Bit
Monitoring. Control bit, when set to a logic 1,
causes the RDI-P to detect G1[3:1] bits for an
enhanced failure code; otherwise, monitors G1[3]
for a 1-bit code.
Receive FORCE_LOP. Control bits, when set to a
logic 1, force the associated time slot into the LOP
state; otherwise, does nothing.
Concatenation Indication Expected. Control bits,
when set to 0 = do not expect associated time slot
to be in CONC mode; otherwise, expect CONC
mode.
Function
†
Agere Systems Inc.
Data Sheet
May 2001
Default
Reset
0x000
0x0
00
0
0
0
0
0