tdat04622 ETC-unknow, tdat04622 Datasheet - Page 66

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 5
* I
38
AM20
AN20
AK31
AL34
u
AM8
W33
W35
AN8
Pin
= I
d
= 50 kΩ, where I
.
Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
RxCLK[D]
RxCLK[C]
RxCLK[B]
RxCLK[A]
RxSZ[D]
RxSZ[C]
RxSZ[B]
RxSZ[A]
Symbol
u
= internal pull-up resistance and I
(continued)
(5 V tolerant)
Type
3.3 V
3.3 V
I
I/O*
u
O
/O Receive Clock. This clock is used to read cells or packets from
the receive FIFO. RxCLK[D:A] can operate at speeds from dc to
104 MHz. For clock rates above 52 MHz, the receive clock must
be placed in source mode.
RxCLK[D:A] sourcing from the respective TxCLK[D:A] may be
provisioned by CLOCK_MODE_Rx (see registers 0x020F,
0x0213, 0x0217, 0x021B on pages 114—115).
In U3 or U3+ (32-bit mode), only the RxCLK[A] input/output pin of
port A is used to clock the data output.
If MPHY mode is used, then all clocks RxCLK[D:A] must be pro-
vided.
Receive Size. These pins are used only in U2+ and U3+ (packet)
modes. This signal defines the valid bytes received and their
packing within (1) RxDATA[D:A][15:0] for U2+ 16-bit mode, and (2)
RxDATA[A][15:0] and RxDATA[B][15:0] for the U3+ (32-bit mode).
The meaning of these bits may be inverted through UT register
0x0226 TxSIZE/RxSIZE mode, page 164.
In U3+ (8-bit mode), RxSZ[D:A] are unused.
For U2+ 16-bit mode,
In U3+ (32-bit mode), the MSByte will be placed on RxDATA[A],
bits 15 to 8. In the 16-bit mode, the MSByte will be placed on
RxDATA[D:A], bits 15 to 8.
For U3+ (32-bit mode), RxSZ[A] and RxSZ[B] are combined to
define four states of the received data stream. RxSZ[C] and
RxSZ[D] are unused. The following states are assigned by
RxSZ[A] and RxSZ[B] when RxEOP[A] is asserted and the
default configuration is provisioned.
RxSZ[A] RxSZ[B]DATA[31:24] DATA[23:16]
The data bytes are packed into the upper transmitted bytes first.
d
= internal pull-down resistance.
0
0
1
1
RxSZ[D:A] = 0 defines the MSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][15:8], to be the last byte of the packet received
when using the default configuration.
RxSZ[D:A] = 1 defines the LSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][7:0], to be the last byte of the packet received
when using the default configuration.
RxDATA[A][15:8] RxDATA[A][7:0]
0
1
0
1
RxDATA[A]
Valid
Valid
Valid
Valid
Name/Description
Not valid
Valid
Valid
Valid
RxDATA[B][15:8] RxDATA[B][7:0]
DATA[15:8]
Not valid
Not valid
Valid
Valid
RxDATA[B]
Agere Systems Inc.
DATA[7:0]
Not valid
Not valid
Not valid
Data Sheet
Valid
May 2001