tdat04622 ETC-unknow, tdat04622 Datasheet - Page 52

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information
Table 3. Pin Descriptions—Line Interface Signals (continued)
Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-
ered to be NC (no connect).
* I
† This may be obtained from a passive voltage divider of a 130 Ω resistor connected from V
24
Note: The TDAT042G5 has internal circuitry that is associated with the buffer section of the chip. This section
u
which is connected to GND
AG3
AG4
Pin
W5
W4
H4
= I
d
= 50 kΩ, where I
monitors the voltage levels of REFLO and REFHI. A very low frequency calibration process, during which
the values at the ECLREFLO and ECLREFHI pins are continuously monitored, is performed to allow the
drive capactity of remaining buffers to be adjusted within true PECL levels. Therefore, it is important to ter-
minate the ECLREFLO and ECLREFHI outputs in exactly the same way as you would terminate LVPECL
outputs.
ECLREFLO
ECLREFHI
RxD[15]P/
RxD[15]N/
RxD[B]P
RxD[B]N
Symbol
CLKDIV
u
= internal pull-up resistance and I
(continued)
D
(5 V tolerant)
.
LVPECL
3.3 V
Type
—
—
I/O*
O
O
I
I
u
Receive Line Data Input [15]/Receive Line Data Input
Channel B. In STS-48/STM-16 mode, these pins function as
receive line data input [15] at 155.52 Mbits/s.
In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line data input channel B at either 155.52 Mbits/s
(STS-3/STM-1) or 622.08 Mbits/s (STS-12/STM-4).
This buffer is internally disabled when not in STS-48/STM-16
mode and channel B is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.
Clock Division. This pin controls a divider in the line transmit
block to create a 77.76 MHz clock from either the 155.52 MHz
STS-3/STM-1 or STS-48/STM-16 transmit line clock, or the
622.08 MHz STS-12/STM-4 transmit line clock, TxCKP/N.
CLKDIV = 1 for STS-12/STM-4 (divide by 8).
CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2).
Reference Voltage for LVPECL I/O Buffers. ECLREFLO and
ECLREFHI are buffer outputs which provide the reference for the
output level of the LVPECL output buffers. ECLREFLO and ECL-
REFHI must be connected to a 50 Ω source of V
user-accessible signal is present on these pins.
d
= internal pull-down resistance.
Name/Description
DDD
to one end of an 82 Ω resistor, the other end of
Agere Systems Inc.
DDD
– 2 V.
Data Sheet
May 2001
†
No