tdat04622 ETC-unknow, tdat04622 Datasheet - Page 290

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Interface Timing Specifications
Microprocessor Interface Timing
Asynchronous Mode (continued)
ADDR[15:0] The address must be valid when ADS is low.
DATA[15:0]
R/W (Input)
CS (Input)
DT (Output) Data transfer acknowledge (active-low). DT is driven asynchronously based on the arrival of CS, DS,
ADS (Input) Address strobe is active-low. The microprocessor can pull ADS high after DT goes high.
DS (Input)
262
Figure 41. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0)
ADDR[15:0]
DATA[15:0]
Read data becomes available after DT goes low. It will be 3-stated when ADS goes high.
The read (H) write (L) signal is always high during a read cycle.
Chip select is an active-low signal.
and ADS. DT is driven high while the internal bus transaction is in progress. There is no need to pro-
vide synchronization to outgoing signals in this mode. DT is driven high and then placed in a high-
impedance state when either ADS or DS is deasserted. DT will become 3-stated when CS is high.
Data strobe is active-low.
ADS
R/W
CS
DS
DT
HIGH Z
t33
t35
t31
t37
HIGH Z
(continued)
t38
(continued)
t41
t36
t39
t34
t42
t32
t40
HIGH Z
HIGH Z
Agere Systems Inc.
Data Sheet
May 2001
5-7662(F)r.6