tdat04622 ETC-unknow, tdat04622 Datasheet - Page 83

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

Data Sheet
May 2001
Agere Systems Inc.
Functional Description
Overhead Processor (OHP) Block
Receive OHP (continued)
B1 BIP-8 Check. The SBIP block counts section BIP-8 (B1) errors. The SBIP value is calculated over the scram-
bled data of the complete previous frame. The calculated value is compared against the received B1 byte and dif-
ferences (errors) are counted. A theoretical maximum of 64,000 errors may be detected per second. The SBIP
block accumulates these errors in a 16-bit saturating counter. This counter operates in latch and clear mode to
ensure Bellcore and ITU compliance with regard to not missing any events (bit errors). It is intended that this
counter be polled at least once per second so that no error events are missed. Optionally, a maximum of only
one SBIP error per frame can be counted (provisionable via B1BITBLKCNT[A—D]; see register description,
page 174). This causes the error counter to only increment by one when one or more errors are detected.
B2 BIP-N Check. The LBIP block counts line BIP-N errors. The LBIP value is calculated over the incoming frame
and is compared to the received B2 bytes received in the next frame. The errors are counted. Optionally, a maxi-
mum of only one LBIP error per frame can be counted (B2BITBLKCNT[A—D]; see register description, page 174).
This causes the block error counter to only increment by one when one or more errors are detected. A theoretical
maximum of 3,072,000 errors may be detected per second. The LBIP block accumulates these errors in a 22-bit
saturating counter. This counter is operated in latch and clear mode to ensure Bellcore and ITU compliance with
regard to not missing any events (bit errors). It is intended that this counter be polled at least once per second so
that no error events are missed.
BER Check. The OHP block also detects provisionable signal fail (SF) and signal degrade (SD) conditions. The
SF and SD values are provisioned through a group of software registers (SF addresses 0x0452—0x0469,
SD addresses 0x043A—0x0451). The SF alarm can be provisioned for a bit error rate (BER) of between 10
10
–5
; the SD alarm can be provisioned for a bit error rate (BER) of between 10
(continued)
(continued)
155/622/2488 Mbits/s Data Interface
–5
to 10
TDAT042G5 SONET/SDH
–9
(see Table 86, page 187).
–3
to
55