tdat04622 ETC-unknow, tdat04622 Datasheet - Page 204

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Register Descriptions
OHP Registers
Table 79. Registers 0x0422—0x042D: Receive Control (R/W) (continued)
Reset default of registers = 0x0000.
176
042B—042D 15—4
Address
(Hex)
Bit #
3
2
1
0
(continued)
RTOAC_OEPINS[B—D]
RTOACSINH[B—D]
RTOACCINH[B—D]
RTOACDINH[B—D]
(continued)
Name
—
Reserved. These bits must be written to their
reset default value (0x000).
Receive TOAC Frame (Sync) Inhibit Channel
[B—D]. When set to 1, the TOAC sync output,
RxTOHF (pins AL3, AN5, AP6), is placed in the
high-impedance state.
Receive TOAC Clock Inhibit Channel [B—D].
When set to 1, the TOAC clock output,
RxTOHCK (pins AL4, AL6, AL7), is placed in
the high-impedance state.
Receive TOAC Data Inhibit Channel [B—D].
When set to 1, the TOAC data output, RxTOHD
(pins AM5, AM6, AN7), is placed in the high-
impedance state.
Receive TOAC Odd or Even Parity Insert
Channel [B—D]. When set to 1, the output
TOAC parity bit is even. When set to 0, the par-
ity is odd.
Function
Agere Systems Inc.
Data Sheet
May 2001
Default
Reset
0x000
0
0
0
0