tdat04622 ETC-unknow, tdat04622 Datasheet - Page 132

• Manufacturer Part Number: tdat04622
• Description: Tdat Sonet/sdh 155/622/2488 Mbits/s Data Interfaces
• Manufacturer: ETC-unknow

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface
Interface Description
Reset
If the reset pin RST (C7) is forced low, the software registers will be placed in their default powerup state. The
device will lose its previous state, and data path continuity will be lost. An internal 100 kΩ pull-up and a Schmitt-
trigger input is provided for this pin. Reset can be generated from software by writing 0x0005 to the core resets reg-
ister (0x000E; see register description on page 149 and timing on page 263).
Performance Monitor Reset (PMRST)
A 1 Hz clock (PMRST) is provided to all internal macrocells. This clock is used to control the 1-second binning of
coding violations (CVs) and alarms. The source of this clock is selectable from one of the three following sources:
I
I
I
This is configured by the line provisioning register (address 0x0010). When under software control, writing 0x0080
to core resets register (address 0x000E) will generate a PMRSTX pulse.
104
The PMRST pin (D7)
A software controllable register (0x000E; see register description on page 149)
An internal 1-second counter (sourced from the 77.76 MHz transmit clock).
000A
000C BLOCK INTERRUPT MASKS
000E
000F
001F
0000
0001
0002
0003
0004
0005
0008
0010
0011
0012
0013
COMPOSITE INTERRUPTS
LOOPBACK CONTROL
LINE PROVISIONING
CHANNEL CONTROL
CORE REGISTERS
DEVICE VERSION
GPIO OUTPUTS
DEVICE NAME =
TDAT042G5
CORE RESETS
GPIO INPUTS
GPIO MODE
SCRATCH
(continued)
Figure 31. Miscellaneous Functionality
PMRST I/O CONTROL
LINE PROVISIONING
LINE EQ./UNEQ.
CORE RESETS
INTERRUPTS
LOOPBACKS
15
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L
A
B
11
A
LB
B
10
P M S
B
PM
C
L
7 6 5 4 3 2 1 0
B
9
C
48
EDGE
POS.
DET.
12
D
L
B
COUNT
1 SEC.
12 12 12
R R R
8
D
RST
DELTA
Agere Systems Inc.
PMRST
Data Sheet
May 2001
5-7060(F)r.4