SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 101

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.10.1
ARM DDI 0165B
Data interface, nonsequential cycles
A memory controller for the ARM9E-S must commit to a data memory access only on
an N cycle or an S cycle.
The ARM9E-S data interface has four types of memory cycle:
Nonsequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer cycle
A nonsequential cycle is the simplest form of an ARM9E-S data interface cycle, and
occurs when the ARM9E-S requests a transfer to or from an address that is unrelated to
the address used in the preceding cycle. The memory controller must initiate a memory
access to satisfy this request.
The address class signals and the DnMREQ and DSEQ
the data bus. At the end of the next bus cycle the data is transferred between the CPU
and the memory. This is shown in Figure 4-9 on page 4-26.
Copyright © 2000 ARM Limited. All rights reserved.
During this cycle the ARM9E-S core requests a transfer to or from
an address that is unrelated to the address used in the preceding
cycle.
During this cycle the ARM9E-S core requests a transfer to or from
an address that is one word greater than the address used in the
preceding cycle.
During this cycle the ARM9E-S core does not require a transfer
because it is performing an internal function.
During this cycle the ARM9E-S core uses the data bus to
communicate with a coprocessor, but does not require any action
by the memory system.
= N cycle
are broadcast on
Memory Interface
4-25