SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 4

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
iv
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Device Reset
Interrupts
ARM9E-S Coprocessor Interface
3.1
3.2
3.3
Memory Interface
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
Copyright © 2000 ARM Limited. All rights reserved.
About device reset ...................................................................................... 3-2
Reset modes .............................................................................................. 3-3
ARM9E-S behavior on exit from reset ........................................................ 3-5
About the memory interface ....................................................................... 4-2
Instruction interface .................................................................................... 4-3
Instruction interface addressing signals ..................................................... 4-4
Instruction interface data timed signals ...................................................... 4-6
Endian effects for instruction fetches .......................................................... 4-7
Instruction interface cycle types ................................................................. 4-8
Data interface ........................................................................................... 4-13
Data interface addressing signals ............................................................ 4-15
Data interface data timed signals ............................................................. 4-18
Data interface cycle types ........................................................................ 4-24
Endian effects for data transfers ............................................................... 4-30
Use of CLKEN to control bus cycles ......................................................... 4-31
About interrupts .......................................................................................... 5-2
Hardware interface ..................................................................................... 5-3
Maximum interrupt latency ......................................................................... 5-7
Minimum interrupt latency .......................................................................... 5-8
About the coprocessor interface ................................................................. 6-2
LDC/STC .................................................................................................... 6-4
MCR/MRC .................................................................................................. 6-8
MCRR/MRRC ........................................................................................... 6-10
Interlocked MCR ....................................................................................... 6-12
Interlocked MCRR .................................................................................... 6-13
CDP .......................................................................................................... 6-14
Privileged instructions ............................................................................... 6-16
Busy-waiting and interrupts ...................................................................... 6-17
Coprocessor 15 MCRs ............................................................................. 6-18
Connecting coprocessors ......................................................................... 6-19
ARM DDI 0165B