SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 123

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.2.1
ARM DDI 0165B
Coprocessor handshake encoding
LAST
Table 6-1 shows how the handshake signals CHSD[1:0] and CHSE[1:0] are encoded.
Copyright © 2000 ARM Limited. All rights reserved.
state of the PASS signal before actually committing to the instruction.
For an
handshake signals with GO when two or more words still have to be
transferred. When only one further word is to be transferred, the
coprocessor drives the handshake signals with LAST. During the Execute
stage, the ARM9E-S processor core outputs the address for the
STC
memory system that a memory access is required at the data end of the
device. The timing for the data on RDATA[31:0] for an
WDATA[31:0] for an
An
case, possibly after busy waiting, the coprocessor drives the coprocessor
handshake signals with a number of GO states, and in the penultimate
cycle drives LAST (LAST indicating that the next transfer is the final
one). If there is only one transfer, the sequence is
[WAIT,[WAIT,...]],LAST.
LDC
. Also in this cycle, DnMREQ is driven LOW, indicating to the
LDC
or
STC
or
STC
can be used for more than one item of data. If this is the
instruction, the coprocessor instruction drives the
STC
is shown in Figure 4-1 on page 4-4.
Handshake
signal
ABSENT
WAIT
GO
LAST
Table 6-1 Handshake signals
ARM9E-S Coprocessor Interface
CHSD[1:0],
CHSE[1:0]
10
00
01
11
LDC
and
LDC
or
6-7