SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 268

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C.10
C.10.1 Register map
C-28
EmbeddedICE-RT logic
The EmbeddedICE-RT logic is integral to the ARM9E-S processor core. It has two
hardware breakpoint or watchpoint units, each of which can be configured to monitor
either the instruction memory interface or the data memory interface. Each watchpoint
unit has registers that set the address, data, and control fields for both values and masks.
The registers used are shown in Table C-4.
Because the ARM9E-S processor core has a Harvard Architecture, you must specify
whether the watchpoint unit examines the instruction or the data interface. This is
specified by bit 3 of the control value register:
•
•
There cannot be a don’t care case for this bit because the comparators cannot compare
the values on both buses simultaneously. Therefore, bit 3 of the control mask register is
always clear and cannot be programmed HIGH. Bit 3 also determines whether the
internal IBREAKPT or DWPT signal must be driven by the result of the comparison.
Figure C-7 on page C-30 gives an overview of the operation of the EmbeddedICE-RT
logic.
The ARM9E-S EmbeddedICE-RT logic has dedicated hardware that allows
single-stepping through code. This reduces the work required by an external debugger,
and removes the need to flush the instruction cache. There is also hardware to allow
efficient trapping of accesses to the exception vectors. These blocks of logic free the
two general-purpose hardware breakpoint or watchpoint units for use by the
programmer at all times.
The general arrangement of the EmbeddedICE-RT logic is shown in Figure C-7 on
page C-30.
The EmbeddedICE-RT logic register map is shown in Table C-4.
Address
00000
00001
00010
00100
when bit 3 is set, the data interface is examined
when bit 3 is clear, the instruction interface is examined.
Copyright © 2000 ARM Limited. All rights reserved.
Width
6
5
8
6
Table C-4 ARM9E-S EmbeddedICE-RT logic register map
Function
Debug control
Debug status
Vector catch control
Debug comms control
Type
Read/write
Read-only
Read/write
Read-only
ARM DDI 0165B
a