SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 149

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5.3
ARM DDI 0165B
WDATA[31:0]
RDATA[31:0]
DBGDEWPT
INSTR[31:0]
DBGACK
DA[31:0]
InMREQ
CLK
Watchpoints
Entry into debug state following a watchpointed memory access is imprecise. This is
necessary because of the nature of the pipeline.
You can build external logic, such as external watchpoint comparators, to extend the
functionality of the EmbeddedICE-RT logic. You must apply their output to the
DBGDEWPT input. This signal is ORed with the internally-generated Watchpoint
signal before being applied to the ARM9E-S core control logic.
The timing of the DBGDEWPT input makes it unlikely that data-dependent external
watchpoints are possible.
After a watchpointed access, the next instruction in the processor pipeline is always
allowed to complete execution. Where this instruction is a single-cycle data-processing
instruction, entry into debug state is delayed for one cycle while the instruction
completes. The timing of debug entry following a watchpointed load in this case is
shown in Figure 7-5.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Figure 7-5 Watchpoint entry with data processing instruction
Debug Interface and EmbeddedICE-RT
7-11