SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 75

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3
ARM DDI 0165B
ARM9E-S behavior on exit from reset
INSTR[31:0]
DnMREQ
nRESET
DA[31:0]
InMREQ
DMORE
IA[31:1]
DnRW
DSEQ
ISEQ
CLK
When nRESET is driven LOW, the currently executing instruction terminates
abnormally. InMREQ, ISEQ, DnMREQ, DSEQ, and DMORE change
asynchronously to indicate an internal cycle. When nRESET is driven HIGH, the
ARM9E-S starts requesting instructions from memory again once the nRESET signal
has been registered, and the first memory access starts two cycles later. The nRESET
signal is sampled on the rising-edge of CLK.
The behavior of the memory interface coming out of reset is shown in Figure 3-2.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 3-2 ARM9E-S behavior on exit from reset
Device Reset
3-5