SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 104

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4-28
The types of bursts are shown in Table 4-16.
All accesses in a burst are of the same width, direction, and protection type. For more
details, see Instruction interface addressing signals on page 4-4.
An example of a burst access is shown in Figure 4-11.
The DMORE signal is active during load and store multiple instructions and only ever
goes HIGH when DnMREQ is LOW. This signal effectively gives the same
information as DSEQ, but a cycle ahead. This information is provided to allow external
logic more time to decode sequential cycles.
Burst type
Word read
Word write
CLK
Address class
signals
DnMREQ
DSEQ
DMORE
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
Copyright © 2000 ARM Limited. All rights reserved.
Address increment
4 bytes
4 bytes
Address
N cycle
Figure 4-11 Sequential access cycles
Address + 4
Write data 1
data 1
Read
Cause
LDM instruction
STM instruction
S cycle
Table 4-16 Burst types
Write data 2
data 2
Read
ARM DDI 0165B