SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 111

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.2
5.2.1
5.2.2
5.2.3
ARM DDI 0165B
Hardware interface
Generating an interrupt
Synchronization
Re-enabling interrupts after an interrupt exception
The hardware interrupt is described under the following headings:
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•
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You can make the ARM9E-S take the FIQ or IRQ exceptions (if interrupts are enabled
within the core) by asserting (LOW) the nFIQ or nIRQ inputs, respectively.
It is essential that once asserted, the interrupt input remains asserted until the ARM9E-S
has completed its interrupt exception entry sequence. When an interrupt input is
asserted, it must remain asserted until the ARM9E-S acknowledges to the source of the
interrupt that the interrupt has been taken. This acknowledgement normally occurs
when the interrupt service routine accesses the peripheral causing the interrupt, for
example:
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•
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The nFIQ and nIRQ inputs are synchronous inputs to the ARM9E-S, and must be setup
and held about the rising edge of the ARM9E-S clock, CLK. If interrupt events that are
asynchronous to CLK are present in a system, synchronization register(s) that are
external to the ARM9E-S are required.
You must take care when re-enabling interrupts (for example at the end of an interrupt
routine or with a reentrant interrupt handler). You must ensure that the original source
of the interrupt has been removed before interrupts are enabled again on the ARM9E-S.
If you cannot guarantee this, the ARM9E-S might retake the interrupt exception
prematurely.
When considering the timing relation of removing the source of interrupt and
re-enabling interrupts on the ARM9E-S, you must take into account the pipelined
nature of the ARM9E-S and the memory system to which it is connected. For example,
the instruction that causes the removal of the interrupt request (that is, deassertion of
Generating an interrupt
Synchronization
Re-enabling interrupts after an interrupt exception
Interrupt registers on page 5-5.
by reading an interrupt status register in the systems interrupt controller
by writing to a clear interrupt control bit
by writing data to, or reading data from the interrupting peripheral.
Copyright © 2000 ARM Limited. All rights reserved.
Interrupts
5-3