SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 130

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SAM9XE512

Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9XE512

Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
ARM9E-S Coprocessor Interface
6.7
6-14
CDP
CDP
InMREQ is driven LOW to signal when an instruction is entering the Decode stage and
again when it reaches the Execute stage of the pipeline:
Figure 6-7 shows a
Abort.
CDP: ARM processor pipeline
CDP: Coprocessor pipeline
instructions normally execute in a single cycle. Like all the previous cycles,
LATECANCEL
if the coprocessor can accept the instruction for execution, the PASS signal is
driven HIGH during the Execute cycle
if the coprocessor can execute the instruction immediately it drives CHSD[1:0]
with LAST
if the instruction requires a busy-wait cycle, the coprocessor drives CHSD[1:0]
with WAIT and then CHSE[1:0] with LAST.
INSTR[31:0]
LDR with Data Abort
CHSD[1:0]
CHSE[1:0]
Copyright © 2000 ARM Limited. All rights reserved.
DABORT
InMREQ
PASS
CLK
CDP
which is canceled due to the previous instruction causing a Data
CPRT
Execute
Decode
Decode
LAST
Memory
Execute
Execute
Figure 6-7 ARM9E-S late-canceled CDP
Ignored
(latecancelled)
Exception
entry start
Memory
Exception
continues
ARM DDI 0165B

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