SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 30

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Introduction
1.4.1
1-12
Operation
Move
Arithmetic
ARM instruction set summary
Move
Move NOT
Move SPSR to register
Move CPSR to register
Move register to SPSR
Move register to CPSR
Move immediate to SPSR flags
Move immediate to CPSR flags
Add
Add with carry
Subtract
Subtract with carry
Reverse subtract
Reverse subtract with carry
Multiply
Multiply accumulate
Multiply unsigned long
Multiply unsigned accumulate long
Multiply signed long
Multiply signed accumulate long
Compare
Compare negative
Saturating add
The ARM instruction set summary is given in Table 1-2.
Copyright © 2000 ARM Limited. All rights reserved.
Assembler
MOV{cond}{S} Rd, <Oprnd2>
MVN{cond}{S} Rd, <Oprnd2>
MRS{cond} Rd, SPSR
MRS{cond} Rd, CPSR
MSR{cond} SPSR{field}, Rm
MSR{cond} CPSR{field}, Rm
MSR{cond} SPSR_flg, #32bit_Imm
MSR{cond} CPSR_flg, #32bit_Imm
ADD{cond}{S} Rd, Rn, <Oprnd2>
ADC{cond}{S} Rd, Rn, <Oprnd2>
SUB{cond}{S} Rd, Rn, <Oprnd2>
SBC{cond}{S} Rd, Rn, <Oprnd2>
RSB{cond}{S} Rd, Rn, <Oprnd2>
RSC{cond}{S} Rd, Rn, <Oprnd2>
MUL{cond}{S} Rd, Rm, Rs
MLA{cond}{S} Rd, Rm, Rs, Rn
UMULL{cond}{S} RdLo, RdHi, Rm, Rs
UMLAL{cond}{S} RdLo, RdHi, Rm, Rs
SMULL{cond}{S} RdLo, RdHi, Rm, Rs
SMLAL{cond}{S} RdLo, RdHi, Rm, Rs
CMP{cond} Rd, <Oprnd2>
CMN{cond} Rd, <Oprnd2>
QADD{cond} Rd, Rn, Rs
Table 1-2 ARM instruction set summary
ARM DDI 0165B