SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 288

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Index
CFGHIVECS
CHAIN
CHSD
CHSE
CLK
CLKEN
Clock
Code density
Cold reset
Compression, instruction
Condition code flags
Configuration input timing
Control bits
Coprocessor
Coprocessor instructions
Core diagram, ARM9E-S
CORECLKENIN
CORECLKENOUT
CPSR
CPU reset
Current program status register
Cycle
D
DA
DABORT
Data
DBGACK
Index-ii
domains
maximum skew
system
test
expansion interface signals
handshake signals
interface
MCR
register transfer cycle
register transfer instructions
Busy-wait
during busy-wait
during interrupts
privileged instructions
privileged modes
mode
internal
merged I-S
nonsequential
sequential
Abort
dependencies
interface
memory interface timing
types
A-4
A-2
2-9, 2-12, 2-14, 2-16
A-7
A-7
C-42
7-14
2-12, 2-14, 2-16
A-2
2-7
6-18
C-25
3-3
3-4
2-23, C-27
A-4
A-9
7-14
2-17
4-9, 4-11
7-14
1-5
6-2
4-13
A-6
4-9
6-6
4-11
A-2
1-4
4-9
A-2
9-8
2-16
6-17
6-17
6-16
6-6
1-5
1-7
4-29
6-16
9-4
9-3
2-9,
B-2
7-16
Copyright © 2000 ARM Limited. All rights reserved.
DBGCOMMRX
DBGCOMMTX
DBGDEWPT
DBGEN
DBGEXT
DBGIEBKPT
DBGINSTREXEC
DBGINSTRVALID
DBGIR
DBGnTDOEN
DBGnTRST
DBGRNG
DBGRQI
DBGSCREG
DBGSDIN
DBGTAPSM
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
Debug
Decode
Determining
Device identification code
Device reset
Disabling EmbeddedICE-RT
DLOCK
DMAS
DMORE
DnM
DnMREQ
DnRW
DnTRANS
DSEQ
comms control register
comms data read register
comms data write register
control register
entry from ARM state
entry from Thumb state
expansion signals
extensions
hardware extensions
interface
interface signals
Multi-ICE
request
state
state, processor restart on exit
status register
support
core state
system state
A-5
A-5
A-5
A-4
1-2
A-8
A-9
A-4
7-5
A-4
A-8
A-9
A-9
A-4
A-8
A-8
A-9
A-8
A-5
C-24
7-6
3-2
3-2, A-8
7-2
A-8
A-8
A-8
A-4
A-3
7-15
7-14
A-8
7-2
A-9
7-15
A-9
7-6
A-9
7-6
A-9
7-5
B-6
7-4
C-9, C-10
C-18
7-16
C-18
7-8
7-16
7-16
C-9
E
EDBGRQ
EmbeddedICE-RT
Endian effects
Endianness
Exception
Exceptions
Execute
F
F bit, FIQ disable
Fetch
FIQ
Flags
Forwarding
Functional diagram, ARM9E-S
H
Halfword
Halfword access
High registers
I
I bit, IRQ disable
IA
IABORT
ID register
IDCODE instruction
Identification register See ID register
InM
debug status register
disabling
functionality
hardware
logic
operation
overview
programming
register map
registers, accessing
reset
single stepping
entry and exit
entry, ARM state
entry, Thumb state
priority
vectors
FIQ
IRQ
disable, F bit
exception
mode
A-3
A-3
2-16
1-2
1-2
2-22
2-22
3-4
A-3
7-4, 7-6
2-7
2-8
A-9
C-5, C-9, C-10
2-20
2-4
2-26
1-4
2-27
7-8
C-28
7-6
7-6
2-22
2-15
4-7, 4-30
4-21
C-28
C-28
2-17
2-17
2-17
C-2
2-20
C-28
C-40
C-5, C-11
2-21
2-21
C-3
7-15
1-7