SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 181

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.12
8.12.1
ARM DDI 0165B
Load register
Interlocks
A load register operation typically occupies the Execute stage for one cycle. There
might be a number of cycles before the loaded value is available for later instructions.
A load to the PC occupies the Execute stage for five cycles.
Destination equals PC is not possible in Thumb state.
The result of an aligned word load instruction is not available until the end of the
Memory stage of the pipeline. If the following instruction requires the use of this result
then it must be interlocked so that the correct value is available. This interlock is
referred to as a single-cycle load-use interlock.
The following example incurs a single-cycle interlock:
LDR r0, [r1]
ADD r2, r0, r3
ORR r4, r4, r5
The following example does not incur an interlock:
LDR r0, [r1]
ORR r4, r4, r5
ADD r2, r0, r3
Unaligned word loads, load byte (
byte rotate unit in the Write stage of the pipeline. This introduces a two-cycle load-use
interlock, that can affect the two instructions immediately following the load
instruction.
The following example incurs a two-cycle interlock:
LDRB r0, [r1, #1]
ADD r2, r0, r3
ORR r4, r4, r5
The following example incurs a single-cycle interlock:
LDRB r0, [r1, #1]
ORR r4, r4, r5
ADD r2, r0, r3
Once an interlock has been incurred for one instruction it does not have to be incurred
for a later instruction.
Note
Copyright © 2000 ARM Limited. All rights reserved.
LDRB
), and load halfword (
LDRH
) instructions use the
Instruction Cycle Times
8-21