SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 226

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Descriptions
A.4
A-6
Miscellaneous signals
The miscellaneous signals are shown in Table A-4.
Name
nFIQ
Not fast interrupt
nIRQ
Not interrupt
request
CFGBIGEND
Big-endian
configuration
CFGDISLTBIT
CFGHIVECS
High vectors
configuration
nRESET
Not reset
FIQDIS
FIQ disabled
IRQDIS
IRQ disabled
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Description
This is the Fast Interrupt Request signal. This input is a
synchronous input to the core. It is not synchronized
internally to the core.
This is the Interrupt Request signal. This input is a
synchronous input to the core. It is not synchronized
internally to the core.
When HIGH, the ARM9E-S processor treats bytes in
memory as being in big-endian format. When it is LOW,
memory is treated as little-endian. This is a static
configuration signal.
When HIGH, the ARM9E-S disables certain ARMv5T
defined behavior involving loading data to the PC. This
input must be tied LOW for normal operation and full
ARMv5T compatibility. This is a static configuration
signal.
When LOW, the ARM9E-S exception vectors start at
address 0x0000 0000. When HIGH the ARM9E-S
exception vectors start at address 0xFFFF 0000. This
is a static configuration signal.
This active LOW reset signal is used to start the
processor from a known address. This is a
level-sensitive asynchronous reset.
When HIGH, indicates that the ARM9E-S is insensitive
to the state of the nFIQ input signal.
When HIGH, indicates that the ARM9E-S is insensitive
to the state of the nIRQ input signal.
Table A-4 Miscellaneous signals
ARM DDI 0165B