SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 233

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
ARM9E-S signal
DBGEXT[1:0]
DBGIEBKPT
DBGINSTREXEC
DBGINSTRVALID
DBGIR[3:0]
DBGnTDOEN
DBGnTRST
DBGRNG[1:0]
DBGRQI
DBGSCREG[4:0]
DBGSDIN
DBGSDOUT
DBGTAPSM[3:0]
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
EDBGRQ
IA[31:1]
INSTR[31:0]
InMREQ
Table B-1 ARM9E-S signals and ARM9TDMI hard macrocell equivalents (continued)
Function
EmbeddedICE EXTERN debug qualifiers (tie LOW when
not required).
External breakpoint (tie LOW when not used).
Instruction executed.
Instruction valid.
TAP controller instruction register.
TDO enable.
TAP controller reset (asynchronous assertion).
EmbeddedICE rangeout qualifier outputs.
Internal status of debug request.
Scan chain register select.
Boundary scan serial data in.
Boundary scan serial data out.
TAP controller state machine state.
Multi-ICE clock input qualifier sampled on the rising edge
of CLK. Used to qualify CLK to enable the debug
subsystem.
Test data input.
Test data output.
Test mode select.
External debug request.
31-bit instruction address output bus, available in the cycle
preceding the Memory cycle.
Instruction data bus used to transfer instructions between
the memory system and the ARM9E-S.
Instruction memory request.
Copyright © 2000 ARM Limited. All rights reserved.
Differences Between the ARM9E-S and the ARM9TDMI
ARM9TDMI hard
macrocell equivalent
EXTERN0, EXTERN1
IEBKPT
INSTREXEC
-
IR[3:0]
nTDOEN
nTRST
RANGEOUT1,
RANGEOUT0
DBGRQI
SCREG[4:0]
SDIN
SDOUT
TAPSM[3:0]
-
TDI
TDO
TMS
EDBGRQ
IA[31:1]
ID[31:0]
InMREQ
Note
-
e
-
-
-
f
f
-
g
-
-
-
-
-
f
f
f
h
c
-
c
B-3