SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 167

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.2
ARM DDI 0165B
Introduction to detailed instruction cycle timings
The pipelined architecture of ARM9E-S overlaps the execution of several instructions
in different pipeline stages. The tables in this section show the number of cycles
required by an instruction, once that instruction has reached the Execute stage of the
pipeline. The instruction cycle count is the number of cycles that an instruction occupies
the execute stage of the pipeline. The other pipeline stages (Fetch, Decode, Memory,
Writeback) are only occupied for one cycle by any instruction (in this model, interlock
cycles are grouped in with the instruction generating the data that creates the interlock
condition, not the instruction dependent on the data).
The request, address, and control signals on both the instruction and data interfaces are
pipelined so that they are generated in the cycle before the one to which they apply, and
are shown as such in the following tables.
The instruction address, IA[31:1], is incremented for prefetching instructions in most
cases. The increment varies with the instruction length:
•
•
The letter i is used to indicate the instruction length.
All cycle counts in this chapter assume zero-wait-state memory access. In a system
where CLKEN is used to add wait states, the cycle counts must be adjusted
accordingly.
Table 8-3 shows the key to the cycle timing tables, Table 8-4 to Table 8-36.
Symbol
pc
pc’
(pc’)
i
-
4 bytes in ARM state
2 bytes in Thumb state.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Meaning
The address of the branch instruction.
The branch target address.
The memory contents of that address.
4 when in ARM state, or 2 when in Thumb state.
Indicates that the signal is not active, and therefore not valid in this cycle.
A blank entry in the table indicates that the status of the signal is not
determined by the instruction in that cycle. The status of the signal is
determined either by the preceding or succeeding instruction.
Table 8-3 Key to cycle timing tables
Instruction Cycle Times
8-7