SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 97

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.9.4
ARM DDI 0165B
Byte and halfword accesses
The ARM9E-S indicates the size of a transfer using the DMAS[1:0] signals. These are
encoded as shown in Table 4-10.
All writable memory in an ARM9E-S based system must support the writing of
individual bytes to allow the use of the C compiler and the ARM debug tool chain (for
example, Multi-ICE).
The address produced by the ARM9E-S is always byte-aligned. However, the memory
system must ignore the insignificant bits of the address. The significant address bits are
listed in Table 4-11.
Reads
When a halfword or byte read is performed, a 32-bit memory system can return the
complete 32-bit word, and the ARM9E-S extracts the valid halfword or byte field from
it. The fields extracted depend on the state of the CFGBIGEND signal, which
determines the endianness of the system (see Memory formats on page 2-4).
Copyright © 2000 ARM Limited. All rights reserved.
DMAS[1:0]
00
01
10
11
DMAS[1:0]
00
01
10
Table 4-11 Significant address bits
Table 4-10 Transfer size encoding
Width
Byte
Halfword
Word
Transfer width
Byte
Halfword
Word
Reserved
Memory Interface
Significant
address bits
DA[31:0]
DA[31:1]
DA[31:2]
4-21