SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 186

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.13
8-26
Store register
A store register operation executes in a single cycle. During the Execute cycle, the store
address is calculated, and the data to be stored is read onto the C bus.
Table 8-22 shows the cycle timing for a store register operation, where:
s
t
Cycle
1
Copyright © 2000 ARM Limited. All rights reserved.
IA
pc+3i
InMREQ,
ISEQ
S cycle
Represents the current mode-dependent value.
Is either 0, when the T bit is specified in the instruction (for
example
STRT
INSTR
(pc+2i)
(pc+3i)
) or s at all other times.
Table 8-22 Store register operation cycle timing
DA
da
DnMREQ,
DSEQ
N cycle
DnTRANS
t
ARM DDI 0165B
WDATA
Rd