SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 223

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

A.2
ARM DDI 0165B
Instruction memory interface signals
The instruction memory interface signals are shown in Table A-2.
Name
IA[31:1]
Instruction address
IABORT
Instruction abort
INSTR[31:0]
Instruction data
DBGIEBKPT
Instruction breakpoint
InMREQ
Not instruction
memory request
InM[4:0]
Instruction mode
InTRANS
Not memory
translate
ISEQ
Instruction Sequential
ITBIT
Instruction Thumb bit
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Input
Input
Input
Output
Output
Output
Output
Output
Table A-2 Instruction memory interface signals
Description
The processor instruction address bus.
This is an input that allows the memory system to
tell the processor that the requested instruction
memory access is not allowed.
This bus is used to transfer instructions between the
memory system and the processor.
This is an input that allows external hardware to
halt the execution of the processor for debug
purposes. If HIGH at the end of an instruction
Fetch it causes the ARM9E-S to enter debug state if
that instruction reaches the Execute stage of the
processor pipeline.
If LOW at the end the cycle, then the processor
requires a memory access during the following
cycle.
These contain the current mode of the processor
and are valid with the address.
When LOW the processor is in User mode, when
HIGH the processor is in a privileged mode. This
signal is valid with the address.
If HIGH at the end of the cycle then any instruction
memory access during the following cycle is
sequential from the last instruction memory access.
When HIGH the processor is in Thumb state, when
LOW the processor is in ARM state. This signal is
valid with the address.
Signal Descriptions
A-3