SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 164

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SAM9XE512

Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9XE512

Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Instruction Cycle Times
8-4
Instruction
LDRD
LDRD
STR
STRD
LDM
LDM
LDM
LDM
LDM
STM
STM
SWP
SWP
PLD
B, BL, BX, BLX
SWI, Undefined
Coprocessor absent
CDP
LDC, STC
MCR
MCRR
MRC
MRC
Cycles
2
3
1
2
2
n
n+1
n+4
5
2
n
2
3
1
3
3
b+4
b+1
b+n
b+1
b+2
b+1
b+2
Copyright © 2000 ARM Limited. All rights reserved.
Instruction
bus
1S+1I
1S+2I
1S
1S+1I
1S+1I
1S+(n-1)I
1S+nI
2S+1N+(n+1)I
2S+2I+1N
1S+1I
1S+(n-1)I
1S+1I
1S+2I
1S
2S+1N
2S+1N
2S+1N+1I+bI
1S+bI
1S+(b+n-1)I
1S+bI
1S+(b+1)I
1S+bI
1S+(b+1)I
Data
bus
1N+1S
1N+1S+1I
1N
1N+1S
1S+1I
1N+(n-1)S
1N+(n-1)S+1I
1N+(n-1)S+4I
1N+4I
1N+1I
1N+(n-1)S
2N
2N+1I
1I
3I
3I
4I+bI
(1+b)I
bI+1N+(n-1)S
bI+1C
bI+2C
bI+1C
(b+1)I+1C
Table 8-2 ARM instruction cycle counts (continued)
Loading n registers, n > 1, not loading the PC.
Loading n registers, n > 1, not loading the PC,
Loaded word used by following instruction.
Comment
Normal case.
Last loaded word used by following
instruction.
All cases.
All cases.
Loading 1 register, not the PC.
last word loaded used by following instruction.
Loading n registers including the PC, n > 0.
Load PC.
Storing 1 register.
Storing n registers, n > 1.
Normal case.
All cases, DnSPEC asserted.
All cases.
All cases.
All cases.
All cases.
All cases.
All cases.
All cases.
Normal case.
Following instruction uses transferred data.
ARM DDI 0165B

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