SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 289

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

InMREQ
INSTR
Instruction
Instruction set
Interface
Interlocking
Internal cycle
Interrupts
Interworking
INTEST
InTRANS
IRQ
ISEQ
ITBIT
J
JTAG instructions
JTAG interface
L
LATECANCEL
Link register
Little-endian
Low registers
LR
compression
coprocessor register transfer
fetch, nonsequential
fetch, sequential
interface
interface cycle types
length
pipeline
pipeline operation
register
SCAN_N
system speed
ARM
summary
Thumb
boundary-scan
debug
disable flags
instruction
mode
disable, I bit
exception
mode
IDCODE
INTEST
RESTART
SCAN_N
SCAN_N TAP
TAP
2-12, 2-14
A-3
A-3
A-3
C-11
A-3
C-16
2-8
1-5, 1-12
A-3
7-2
2-6
1-5
C-9, C-10
1-4
1-2
2-9, 2-12, 2-14
2-4
2-3
C-12
4-3
1-10
4-9, 4-11
2-15
C-5, C-11
C-8, C-12
2-22
C-12, C-16
C-12
C-9
7-4, 7-5
A-7
2-17
1-5
2-21
C-26
C-5
C-14
4-10
1-4
4-9
4-8
7-16
Copyright © 2000 ARM Limited. All rights reserved.
M
MCR
Memory
Merged I-S cycle
Mode
Multi-ICE
N
N flag
nFIQ
nIRQ
Nonsequential cycle
nRESET
O
Operating modes
Operating state
P
PASS
PC
Pipeline
Power-on reset
Prefetch Abort
Priority of exceptions
Privileged modes
Processor state, determining
Program counter
Program status registers
access
cycle
formats
interface
requests, withdrawal of
abort
bits
FIQ
identifier
IRQ
operating
privileged
PSR bit values
supervisor
System
Undefined
User
ARM
T bit
Thumb
ARM
coprocessor
Pipeline follower
2-12, 2-14
A-6
6-18
A-6
A-7
2-16
2-18
2-8
1-2
2-8
3-2, A-6
2-8
2-18
2-8, C-25
4-8
2-3
6-2
7-14
1-4
2-3
2-8
2-4
4-2
2-10
2-8
2-8
2-8
2-23, C-27
2-8
3-3
6-2
2-9, 2-12, 2-14
2-8
4-11
2-8
2-18
4-9
6-2
2-27
2-16
4-32
C-18
PSR
Q
Q flag
R
RDATA
Register
Register, debug
Reserved bits, PSR
Reset
RESTART instruction
Restart on exit from debug
S
Saved program status register
Scan
Scan chains
SCANENABLE
SCANIN
control bits
mode bit values
reserved bits
banked
current program status
general-purpose
high
link
program status
saved program status
status
bypass
comms control
comms data read
comms data write
control
EmbeddedICE-RT debug
EmbeddedICE-RT, accessing
ID
instruction
scan path select
status
test data
behavior
CPU
EmbeddedICE-RT
modes
power-on
warm
cells
path
path select register
number allocation
scan chain 1
scan chain 2
2-22, 3-2
2-17
C-5, C-10
2-9
A-4
C-2
2-15
C-14
3-4
B-5
2-9
7-6
3-4
3-3
C-10
7-6
2-9
C-10
3-5
status
3-3
C-9, C-10
2-17
B-5
C-2, C-10, C-14
C-2, C-10, C-16
2-19
2-16
2-19
7-16
C-8, C-10
2-18
2-9
7-16
7-16
C-9
7-15
C-12
3-4
C-8, C-10
2-9
C-9
2-9
2-9
Index-iii
Index
C-3