SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 156

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7.8.3
7-18
Comms channel monitor mode debug status register
You can use the following instructions to access these registers:
MRC p14, 0, Rd, c0, c0
This returns the debug comms control register into Rd.
MCR p14, 0, Rn, c1, c0
This writes the value in Rn to the comms data write register.
MRC p14, 0, Rd, c1, c0
This returns the debug data read register into Rd.
The Thumb instruction set does not support coprocessor instructions. Therefore, the
processor must be in ARM state before you can access the debug comms channel.
The coprocessor 14 monitor mode debug status register is provided for use by a debug
monitor when the ARM9E-S is configured into the monitor mode debug mode.
The coprocessor 14 monitor mode debug status register is a 1-bit wide read/write
register having the format shown in Figure 7-9.
Bit 0 of the register, the DbgAbt bit, indicates whether the processor took a Prefetch or
Data Abort in the past because of a breakpoint or watchpoint. If the ARM9E-S core
takes a Prefetch Abort as a result of a breakpoint or watchpoint, then the bit is set. If on
a particular instruction or data fetch, both the debug abort and external abort signals are
asserted, the external abort takes priority and the DbgAbt bit is not set. You can read or
write the DbgAbt bit using
Note
Copyright © 2000 ARM Limited. All rights reserved.
Figure 7-9 Coprocessor 14 monitor mode debug status register format
MRC
or
MCR
instructions.
ARM DDI 0165B