SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 79

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.2
4.2.1
ARM DDI 0165B
Instruction interface
Instruction interface signals
The ARM9E-S requests instructions for execution using the instruction memory
interface. A new instruction is fetched over the instruction bus whenever an instruction
enters the Execute stage of the pipeline.
Instruction fetches take place in the Fetch stage of the pipeline.
The signals in the ARM9E-S instruction interface can be grouped into four categories:
•
•
•
•
Each of these signal groups shares a common timing relationship to the bus interface
cycle. All signals in the ARM9E-S instruction interface are generated from, or sampled
by, the rising edge of CLK.
You can extend bus cycles using the CLKEN signal (see Use of CLKEN to control bus
cycles on page 4-31). Unless otherwise stated CLKEN is permanently HIGH.
Clocking and clock control signals:
—
—
—
Address class signals:
—
—
—
—
Memory request signals:
—
—
Data timed signals:
—
—
Copyright © 2000 ARM Limited. All rights reserved.
CLK
CLKEN
nRESET.
IA[31:1]
ITBIT
InTRANS
InM[4:0].
InMREQ
ISEQ.
INSTR[31:0]
IABORT.
Memory Interface
4-3