SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 275

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.10.6 Debug status register
ARM DDI 0165B
Both IRQ and FIQ are disabled when the processor is in debug state (DBGACK =1),
or when INTDIS is forced.
As shown in Figure C-12 on page C-37, the value stored in bit 1 of the control register
is synchronized and then ORed with the external EDBGRQ before being applied to the
processor.
In the case of DBGACK, the value of DBGACK from the core is ORed with the value
held in bit 0 to generate the external value of DBGACK seen at the periphery of the
ARM9E-S. This allows the debug system to signal to the rest of the system that the core
is still being debugged even when system-speed accesses are being performed (in which
case the internal DBGACK signal from the core is LOW).
The structure of the debug control and status registers is shown in Figure C-12 on
page C-37.
The debug status register is five bits wide. If it is accessed for a read (with the read/write
bit LOW), the status bits are read. The format of the debug status register is shown in
Figure C-11.
Copyright © 2000 ARM Limited. All rights reserved.
DBGACK
0
1
x
Figure C-11 Debug status register
Table C-8 Interrupt signal control
INTDIS
0
x
1
Interrupts
Permitted
Inhibited
Inhibited
Debug in depth
C-35