SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 5

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
Chapter 7
Chapter 8
Chapter 9
Debug Interface and EmbeddedICE-RT
AC Parameters
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Instruction Cycle Times
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
9.1
9.2
Copyright © 2000 ARM Limited. All rights reserved.
About the debug interface ........................................................................... 7-2
Debug systems ........................................................................................... 7-3
About EmbeddedICE-RT ............................................................................ 7-6
Disabling EmbeddedICE-RT ....................................................................... 7-8
Debug interface signals .............................................................................. 7-9
ARM9E-S core clock domains .................................................................. 7-14
Determining the core and system state ..................................................... 7-15
The debug communications channel ........................................................ 7-16
Monitor mode debug ................................................................................. 7-21
Instruction cycle count summary ................................................................. 8-3
Introduction to detailed instruction cycle timings ......................................... 8-7
Branch and ARM branch with link ............................................................... 8-8
Thumb branch with link ............................................................................... 8-9
Branch and exchange ............................................................................... 8-10
Thumb Branch, Link, and Exchange <immediate> ................................... 8-11
Data operations ......................................................................................... 8-12
MRS .......................................................................................................... 8-14
MSR operations ........................................................................................ 8-15
Multiply and multiply accumulate .............................................................. 8-16
QADD, QDADD, QSUB, and QDSUB ....................................................... 8-20
Load register ............................................................................................. 8-21
Store register ............................................................................................ 8-26
Load multiple registers .............................................................................. 8-27
Store multiple registers ............................................................................. 8-30
Load double register ................................................................................. 8-31
Store double register ................................................................................. 8-32
Data swap ................................................................................................. 8-33
PLD ........................................................................................................... 8-35
Software interrupt, undefined instruction, and exception entry ................. 8-36
Coprocessor data processing operation ................................................... 8-37
Load coprocessor register (from memory) ................................................ 8-38
Store coprocessor register (to memory) .................................................... 8-40
Coprocessor register transfer (to ARM) .................................................... 8-42
Coprocessor register transfer (from ARM) ................................................ 8-43
Double coprocessor register transfer (to ARM) ......................................... 8-44
Double coprocessor register transfer (from ARM) .................................... 8-45
Coprocessor absent .................................................................................. 8-46
Unexecuted instructions ............................................................................ 8-47
Timing diagrams ......................................................................................... 9-2
AC timing parameter definitions .................................................................. 9-8
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