SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 51

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.7
2.7.1
ARM DDI 0165B
Registers
The ARM state register set
The ARM9E-S has a total of 37 registers:
•
•
These registers are not all accessible at the same time. The processor state and operating
mode determine which registers are available to the programmer.
In ARM state, 16 general registers and one or two status registers are accessible at any
one time. In privileged modes, mode-specific banked registers become available.
Figure 2-3 on page 2-11 shows which registers are available in each mode.
The ARM state register set contains 16 directly-accessible registers, r0 to r15. A further
register, the Current Program Status Register (CPSR), contains condition code flags
and the current mode bits. Registers r0 to r13 are general-purpose registers used to hold
either data or address values. Registers r14, r15, and the CPSR have the following
special functions:
Link register
Program counter
In privileged modes, another register, the Saved Program Status Register (SPSR), is
accessible. This contains the condition code flags and the mode bits saved as a result of
the exception that caused entry to the current mode.
31 general-purpose 32-bit registers
6 32-bit status registers.
Copyright © 2000 ARM Limited. All rights reserved.
Register r14 is used as the subroutine Link Register (LR).
Register r14 receives a copy of r15 when a Branch with Link (
or
You can treat r14 as a general-purpose register at all other times.
The corresponding banked registers r14_svc, r14_irq, r14_fiq,
r14_abt and r14_und are similarly used to hold the return values
of r15 when interrupts and exceptions arise, or when
instructions are executed within interrupt or exception routines.
Register r15 holds the PC.
In ARM state, bits [1:0] of r15 are zero. Bits [31:2] contain the PC.
In Thumb state, bit [0] is zero. Bits [31:1] contain the PC.
BLX
) instruction is executed.
Programmer’s Model
BL
or
BLX
BL
2-9