SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 82

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.4
4.4.1
4.4.2
4-6
Instruction interface data timed signals
INSTR[31:0]
IABORT
The data timed signals for the instruction memory interface are:
•
•
INSTR[31:0] is the read data bus, and is used by the ARM9E-S to fetch opcodes. The
INSTR[31:0] signal is sampled on the rising edge of CLK at the end of the bus cycle.
IABORT indicates that an instruction fetch failed to complete successfully. IABORT
is sampled at the end of the bus cycle during active memory cycles (S cycles and N
cycles).
If IABORT is asserted on an opcode fetch, the abort is tracked down the pipeline, and
the Prefetch Abort trap is taken if the instruction is executed.
IABORT can be used by a memory management system to implement, for example, a
basic memory protection scheme, or a demand-paged virtual memory system.
For more details about aborts, see Aborts on page 2-23.
INSTR[31:0]
IABORT.
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