SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 290

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Index
SCANOUT
SCAN_N
Sequential cycle
Serial interface, JTAG
Signal types
Signals
Index-iv
address class
data timed
debug interface
CFGBIGEND
CFGDISLTBIT
CFGHIVECS
CHAIN
CHSD
CHSE
CLK
CLKEN
CORECLKENIN
CORECLKENOUT
DA
DABORT
DBGACK
DBGCOMMRX
DBGCOMMTX
DBGDEWPT
DBGEN
DBGEXT
DBGIEBKPT
DBGINSTREXEC
DBGINSTRVALID
DBGIR
DBGnTDOEN
DBGnTRST
DBGRNG
DBGRQI
DBGSCREG
DBGSDIN
DBGSDOUT
DBGTAPSM
DBGTCKEN
DBGTDI
DBGTDO
DBGTMS
DLOCK
DMAS
DMORE
DnM
DnMREQ
DnRW
DnTRANS
DSEQ
EDBGRQ
IA
IABORT
InM
InMREQ
INSTR
InTRANS
ISEQ
ITBIT
LATECANCEL
nFIQ
A-3
A-4
A-3
A-2
C-8, C-12, C-16
A-5
A-6
A-3
A-7
A-3
A-5
A-7
A-5
A-4
A-3
B-5
A-8
C-42
A-2
A-9
A-4
A-4
A-3
A-3
A-8
A-9
A-9
A-4
A-4
A-9
A-3
A-8
A-8
4-6, 4-18
A-9
A-9
A-8
A-5
4-9
3-2, A-8
4-4, 4-15
A-8
A-8
A-8
A-8
A-6
A-4
A-3
A-6
A-8
7-5
A-6
A-9
A-7
A-9
A-2
7-4, 7-5
A-9
A-2
A-9
Copyright © 2000 ARM Limited. All rights reserved.
Signals (continued)
Significant address bits
Single-step core operation
Single-stepping
Software interrupt
SP
SPSR
Stack pointer
State
States
State, switching
Status registers
Sticky overflow flag
Stored program status register
Supervisor mode
SWI
Switching states
System mode
System speed instruction
System state, determining
T
T bit
TAP
TAPID
Test Access Port
Test clock
Test data registers
Thumb
Thumb state to ARM state
nIRQ
nRESET
PASS
RDATA
SCANENABLE
SCANIN
SCANOUT
TAPID
WDATA
ARM
debug
Thumb
core
system
TAP
TAP controller
controller
controller, states
instruction
state
instruction set
state
2-12, 2-14
2-24
2-18
7-2
2-9, 2-12, 2-14, 2-16, C-25
A-9
2-14, 2-16
C-18
C-14
1-5, 2-3, 2-12
C-14
A-6
1-5
7-14
A-7
7-5
C-18
1-5
A-9
A-4
2-12, 2-14
3-2, A-6
2-8
B-5
A-4
7-4, C-2, C-3, C-14
C-11
2-9
C-40
2-3
B-5
2-3
7-2
2-8
C-10
2-24
1-5
7-2
2-17
B-5
7-2
4-7
C-26
7-15
C-8
2-3
2-12,
Timing
U
Undefined instruction
Undefined mode
Unused instruction codes
User mode
V
V flag
Vector, exception
W
Warm reset
Watchpointed
Watchpoints
WDATA
Word
Writeback
Z
Z flag
configuration input
data memory interface
exception input
access
memory access
aborted
timing
with exception
2-7
2-16
2-16
A-4
1-2
C-25, C-27
2-8
7-11
3-4
C-26
7-6, 7-7, C-24
2-8
2-26
C-24
C-25
9-4
2-25
9-4
C-9
9-3